Method for provisioning decoupling capacitance in an integrated circuit

Patent metadata

Field	Value
Publication number	US-9465899-B2
Application number	US-201313837565-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A method of provisioning an integrated circuit with decoupling capacitance includes identifying in an initial design of the integrated circuit lacking decoupling elements, a standard cell instance satisfying a transient power or frequency switching criteria. Based on a transient power characteristic of the standard cell instance, a decoupling capacitance requirement for the standard cell instance is determined. The decoupling capacitance requirement indicates a capacitance sufficient to bring the standard cell instance into compliance with a stability constraint on a supply voltage node of the standard cell instance. A decoupling capacitor satisfying the decoupling capacitance requirement is provisioned by appending an appropriate sized decap transistor having one or more gate electrode elements to the standard cell instance. The size of the decap transistor may be derived from the required decoupling capacitance, the amount of decoupling capacitance contributed by each gate electrode element, and the area required for each gate electrode element.

First claim

What is claimed is:

1. A method of provisioning a semiconductor device with decoupling capacitors, the method comprising:
identifying, from data indicative of an initial design of the semiconductor device, standard cell instances satisfying a decoupling criteria, wherein the identifying is performed by a processor;
generating, by the processor, a modified design of the semiconductor device by integrating a decoupling capacitor in the standard cell instances satisfying the decoupling criteria to form modified cell instances,
wherein the integrating the decoupling capacitor comprises extending a boundary of the standard cell instances and adding a decap transistor to form the modified cell instances, wherein the decap transistor implements capacitance of the decoupling capacitor,
wherein each standard cell instance comprises two or more gate structures that are arranged in parallel and are spaced apart from each other by a standard spacing that is a uniform spacing predefined in the standard cell instances,
wherein the decap transistor comprises at least a first gate structure and a second gate structure that are arranged in parallel with the two or more gate structures, wherein the first gate structure is spaced apart form an adjacent one of the two or more gate structures by the standard spacing and spaced apart from the second gate structure by the standard spacing,
wherein the first and second gate structures each traverse at least one active region included within the modified cell instances, wherein the first and second gate structures implement an amount of the capacitance, wherein the amount of the capacitance is proportional to a combined area of the first and second gate structures overlying the at least one active region; and

fabricating, by the processor, the device having the modified design.

2. The method of claim 1 , wherein standard cell instances in the initial design lack decoupling capacitors.

3. The method of claim 1 , wherein standard cell instances in the initial design not satisfying the decoupling criteria lack decoupling capacitors in the modified design.

4. The method of claim 1 , wherein the decoupling criteria identify standard cell instances exceeding a switching frequency threshold.

5. The method of claim 1 , wherein the integrating of a decoupling capacitor includes estimating the capacitance of the decoupling capacitor required to bring the standard cell instance into compliance with a specified constraint.

6. The method of claim 5 , wherein the specified constraint comprises a voltage stability constraint indicating a maximum acceptable variation of a supply voltage node of the standard cell instance.

7. The method of claim 5 , wherein a size of the decap transistor corresponds to an amount of the capacitance.

8. The method of claim 5 , wherein the two or more gate structures are arranged in an order having a first end and a second end and wherein the adding the decap transistor includes adding N new gate structures to the order, wherein N is an integer greater than 0 determined based on the capacitance estimated, wherein the N new gate structures comprises the first and second gate structures.

9. The method of claim 8 , wherein the N new gate structures and the two or more gate structures each have a same standard width and length that is a uniform width and length predefined in the standard cell instances.

10. The method of claim 8 , wherein adding the N new gate structures comprises adding a first portion of the N new gates structures adjacent to the first end of the order and adding a remaining portion of the N new gates structures to the second end of the order, wherein each of the N new gate structures are spaced from each other and from either end of the order by the standard spacing.

11. The method of claim 8 , wherein the decap transistor comprises a floating gate decap transistor and the N new gate structures comprise N floating gate structures.

12. The method of claim 8 , wherein the decap transistor comprises a biased gate decap transistor and the N new gate structures comprise N biased gate structures.

13. The method of claim 8 , wherein the plurality of gate structures include a complementary gate structure, wherein the complementary gate structure includes a gate structure comprising a first portion overlying a p-type active region and a second portion overlying an n-type active region.

14. A semiconductor device, comprising:
a plurality of standard cell instances including noisy standard cells instances and quiet standard cell instances; and
decoupling capacitors selectively integrated into a portion of the plurality of standard cell instances to form modified cell instances;
wherein the portion of the plurality of standard cell instances into which the decoupling capacitors are integrated comprise the noisy standard cell instances,
wherein each of the noisy standard cell instances comprises two or more gate structures that are arranged in parallel and are spaced apart from each other by a standard spacing that is a uniform spacing predefined in the plurality of standard cell instances,
wherein the decoupling capacitors comprise decap transistors, each decap transistor having at least a first gate structure and a second gate structure that are arranged in parallel with the two or more gate structures, wherein the first gate structure is spaced apart from an adjacent one of the two or more gate structures by the standard spacing and spaced apart from the second gate structure by the standard spacing,
wherein the first and second gate structures each traverse at least one active region included within the modified cell instances, wherein the first and second gate structures are determined based on a capacitance requirement of a corresponding standard cell instance, wherein the first and second gate structures implement an amount of capacitance indicated by the capacitance requirement, wherein the amount of capacitance is proportional to a combined area of the first and second gate structures overlying the at least one active region.

15. The semiconductor device of claim 14 , wherein each decoupling capacitor comprises a first decap transistor appended to a first end of its standard cell instance.

16. The semiconductor device of claim 15 , wherein each decoupling capacitor further comprises a second decap transistor appended to a second of its standard cell instance.

17. The semiconductor device of claim 14 , wherein the decap transistors comprise floating gate decap transistors.

18. The semiconductor device of claim 14 , wherein the decap transistors comprise biased gate decap transistors.

19. A method of designing an integrated circuit, the method comprising:
identifying, in data indicative design of the integrated circuit, a standard cell instance satisfying a transient power criteria, wherein the identifying is performed by a processor;
determining, based on a transient power characteristic of the standard cell instance, a decoupling capacitance requirement for the standard cell instance, wherein the decoupling capacitance requirement indicates a capacitance sufficient to bring the standard cell instance into compliance with a stability constraint on a supply voltage node of the standard cell instance, and wherein the determining is performed by the processor;
adding, by the processor, a decoupling capacitor satisfying the decoupling capacitance requirement into the standard cell instance to form a modified cell instance,
wherein the decoupling capacitor comprises a decap transistor t

Assignees

• Freescale Semiconductor Inc

Inventors

• Sundareswaran Savithri
• Huang Benjamin S
• Vaidyanathan Ravi K

Classifications

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2217/82

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic