Memory and method for operating a memory with interruptible command sequence

Patent metadata

Field	Value
Publication number	US-10289596-B2
Application number	US-201715411731-A
Country	US
Kind code	B2
Filing date	Jan 20, 2017
Priority date	Jun 7, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

First claim

What is claimed is:

1. A memory device, comprising:
a memory;
a bus interface;
control circuitry to access the memory and execute memory read and write operations;
command logic configured to decode command sequences received on the bus interface that comprise corresponding operation codes, and one or both of addresses and data, received on the bus interface, and to enable the control circuitry to execute operations identified in the command sequences;
while receiving a first command sequence, the command logic being responsive to a first control signal to interrupt the first command sequence;
the command logic being responsive to a second control signal after the first control signal, to receive and decode a second command sequence and to enable the control circuitry to execute an operation identified in the second command sequence;
the command logic responsive to a third control signal after completion of the second command sequence to receive and decode a third command sequence, the third command sequence including an operation code and data, to complete the interrupted first command sequence, and to enable the control circuitry to execute the operation identified in the first command sequence.

2. The memory device of claim 1 , wherein the bus interface is configured for a synchronous serial bus.

3. The memory device of claim 1 , the command logic including a buffer to hold at least portions of the first command sequence, and the command logic decodes the third command sequence using the portions of the first command sequence stored in the buffer.

4. The memory device of claim 1 , wherein the operation code of the first command sequence identifies a write operation, and the operation code of the second command sequence identifies a read operation.

5. The memory device of claim 1 , wherein the operation code of the first command sequence identifies a write operation for which data is received in the bus interface on a particular bus line, and the operation code of the second command sequence identifies a read operation for which the operation code is received in the bus interface on the same particular bus line.

6. The memory device of claim 1 , wherein the operation code of the first command sequence identifies a write operation, and the third command sequence includes the operation code and the address of the first command sequence.

7. The memory device of claim 1 , wherein the operation code of the first command sequence identifies a write operation, and the third command sequence includes a write continue operation code with an address.

8. The memory device of claim 1 , wherein the operation code of the first command sequence identifies a write operation and a write count.

9. The memory device of claim 1 , wherein the command logic is configured to enable embedded operations associated with the first command sequence, in response to a write confirm operation code received on the bus interface, received after the third command sequence.

10. A method for operating a memory device, having a memory including a bus interface and control circuitry to access the memory and execute memory read and write operations, and command logic configured to decode command sequences received on the bus interface that comprise corresponding operation codes, and one or both of addresses and data, received on the bus interface, and to enable the control circuitry to execute operations identified in the command sequences; the method comprising:
while receiving a first command sequence, interrupting the first command sequence in response to a first control signal;
in response to a second control signal after the first control signal, receiving and decoding a second command sequence and enabling the control circuitry to execute an operation identified in the second command sequence;
in response to a third control signal after completion of the second command sequence, receiving and decoding a third command sequence, the third command sequence including an operation code and data, to complete the interrupted first command sequence; and
enabling the control circuitry to execute the operation identified in the first command sequence after receiving the third command sequence.

11. The method of claim 10 , wherein the bus interface is configured for a synchronous serial bus.

12. The method of claim 10 , including storing at least portions of the first command sequence in a buffer, and decoding the third command sequence using the portions of the first command sequence stored in the buffer.

13. The method of claim 10 , wherein the operation code of the first command sequence identifies a write operation, and the operation code of the second command sequence identifies a read operation.

14. The method of claim 10 , wherein the operation code of the first command sequence identifies a write operation for which data is received in the bus interface on a particular bus line, and the operation code of the second command sequence identifies a read operation for which the operation code is received in the bus interface on the same particular bus line.

15. The method of claim 10 , wherein the operation code of the first command sequence identifies a write operation, and the third command sequence includes the operation code and the address of the first command sequence.

16. The method of claim 10 , wherein the operation code of the first command sequence identifies a write operation, and the third command sequence includes a write continue operation code with an address.

17. The method of claim 10 , wherein the operation code of the first command sequence identifies a write operation and a write count, and the third command sequence includes a write continue operation code.

18. The method of claim 10 , wherein the third command sequence includes a write confirm code in a last cycle in the sequence.

19. A memory device, comprising:
a nonvolatile memory;
a synchronous serial bus interface;
control circuitry to access the memory and execute memory read and write operations; and
command logic configured to decode command sequences received on the bus interface that comprise corresponding operation codes, and one or both of addresses and data, received on the bus interface, and to enable the control circuitry to execute operations identified in the command sequences;
while receiving a first command sequence including an operation code for a page write operation, the command logic being responsive to a first control signal to interrupt the first command sequence;
the command logic being responsive to a second control signal after the first control signal, to receive and decode a second command sequence including an operation code for another operation, and to enable the control circuitry to execute the other operation identified in the second command sequence;
the command logic responsive to a third control signal after the second command sequence, to receive and decode a third command sequence, the third command sequence including an operation code and data, to complete the interrupted first command sequence, and to enable the control circuitry to execute the page write operation identified in the first command sequence.

20. The memory device of claim 19 , wherein the data for the page write of the first command sequence is received in the bus interface on a particular bus line, and the operation code of the second command sequence is received in the bus interface on the same particular bus line.

Assignees

• Macronix Int Co Ltd

Inventors

• Chen Ken-Hui
• Chang Kuen-Long
• Lo Su-Chueh
• Liao Chun-Yu

Classifications

• G06F13/1673

  using buffers · CPC title

• G06F13/4234 Primary

  being a memory bus · CPC title

• G06F13/34 Primary

  with priority control · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F13/1631

  through address comparison · CPC title