System and method of arbitrating cache requests

Patent metadata

Field	Value
Publication number	US-10289574-B2
Application number	US-201514853891-A
Country	US
Kind code	B2
Filing date	Sep 14, 2015
Priority date	May 1, 2013
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

This disclosure relates to arbitration of different types of requests to access a cache. Features of this disclosure can be implemented in a graphics processing unit (GPU). In one embodiment, an arbiter can receive requests from a color processor and a depth processor and determine which of the received requests has the highest priority. The request with the highest priority can then be provided to the cache. The priority can be configurable. The arbiter can determine priority, for example, based on whether a location in the cache associated with a request is available, a weight associated with the request, a number of requests of a particular type processed by the arbiter, or any combination thereof.

First claim

I claim:

1. An apparatus comprising:
a cache configured to store data; and
an arbiter comprising electronic hardware, the arbiter configured to:
assign weights to different types of cache requests based on information received by the arbiter;
receive a request of a first type to access the cache;
receive a request of a second type to access the cache;
determine, based on information from the cache, whether a location in the cache associated with the request of the first type or the request of the second type is available, wherein the location in the cache is not available when at least one of data other than requested data is stored in the location or when valid data is not stored in the location;
determine which of the received requests has a higher priority based at least partly on the weights assigned to the first type of request and the second type of request and based at least partly on whether the location in the cache associated with the request of the first type or the request of the second type is available; and
provide the cache with the received request determined to have the higher priority.

2. The apparatus of claim 1 , wherein the arbiter comprises a plurality of input counters, each of the plurality of input counters configured to count a number of requests of a respective one of the different types of cache requests processed by the arbiter.

3. The apparatus of claim 2 , wherein the arbiter is configured to determine the higher priority based at least partly on a comparison of a selected one of the weights assigned to different types of cache requests and the number of requests counted by the corresponding input counter.

4. The apparatus of claim 2 , wherein the apparatus is configured to count how many requests have been provided to the cache.

5. The apparatus of claim 2 , wherein the arbiter is configured to clear the input counters in response to detecting a condition.

6. The apparatus of claim 1 , wherein the apparatus comprises a graphics processing unit, and the graphics processing unit comprises the cache, the arbiter, a depth processor, and a color processor.

7. The apparatus of claim 1 , wherein the different types of cache requests comprise a color read, a color write, a depth read, and a depth write.

8. The apparatus of claim 1 , further comprising a weighting circuit configured to generate the information received by the arbiter for assigning weights to the different types of cache requests.

9. The apparatus of claim 1 , wherein the information received by the arbiter for assigning weights to the different types of cache requests is generated by a driver.

10. An apparatus comprising:
a cache configured to store data;
means for receiving a plurality of cache requests of different types, wherein each cache request of the plurality of cache requests is associated with a type of cache request of the different types of cache requests;
means for determining, based on information from the cache, whether a location in the cache associated with the plurality of cache requests of different types is available, wherein the location in the cache is not available when at least one of data other than requested data is stored in the location or when valid data is not stored in the location;
means for determining which cache request of the plurality of cache requests of the different types has a higher priority based at least partly on weights associated with the different types of cache requests and based at least partly on whether the location in the cache associated with the plurality of cache requests is available; and
means for providing the cache with the cache request determined to have the higher priority.

11. A method of providing a cache request to a cache, the method comprising:
receiving, via an electronic hardware processor, a plurality of cache requests of different types from different requestors to access a cache shared, wherein each cache request of the plurality of cache requests is associated with a type of cache request of the different types of cache requests;
determining, based on information from the cache and via the electronic hardware processor, whether a location in the cache associated with the plurality of cache requests of different types is available, wherein the location in the cache is not available when at least one of data other than requested data is stored in the location or when valid data is not stored in the location;
determining, via the electronic hardware processor, which cache request of the plurality of cache requests of the different types has a higher priority based at least partly on one or more weights associated with the different types of cache requests and based at least partly on whether the location in the cache associated with the plurality of cache requests is available; and
providing, via the electronic hardware processor, the cache request with the higher priority to the cache prior to providing other cache requests of the plurality of cache requests.

12. The method of claim 11 , wherein the plurality of cache requests of different types comprises a color read, a color write, a depth read, and a depth write.

13. The method of claim 11 , further comprising configuring the one or more weights, wherein said configuring is performed at the direction of a driver.

14. The method of claim 11 , further comprising generating counts of cache requests with a counter for each of the cache requests having a different type.

15. The method of claim 14 , further comprising clearing the counts of the number of cache requests of the different types based at least partly on detecting a condition.

16. The method of claim 15 , wherein the condition is indicative of a predetermined number of cache requests being received.

17. A non-transitory computer-readable storage comprising instructions that, when executed, direct a processor to perform a method, the method comprising:
determining, based on information from a cache, whether a location in the cache associated with a plurality of cache requests of different types is available, wherein the location in the cache is not available when at least one of data other than requested data is stored in the location or when valid data is not stored in the location, wherein each cache request of the plurality of cache requests is associated with a type of cache request of the different types of cache requests;
selecting based at least partly on weights associated with the different types of cache requests, a cache request from a plurality of cache requests of the different types having a higher priority, wherein the selecting is based at least partly on an indication of whether the location in the cache associated with the plurality of cache requests is available; and
providing the selected cache request to the cache prior to providing other cache requests of the plurality of cache requests to the cache.

18. The non-transitory computer-readable storage of claim 17 , wherein the method further comprises setting the weights in registers of an arbiter, and wherein the weights are configurable.

Assignees

• Qualcomm Inc

Inventors

• Wang Chunlin

Classifications

• G06F12/084

  with a shared cache · CPC title

• G06F2212/302

  In image processor or graphics adapter · CPC title

• G06F12/0855

  Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence) · CPC title

• G06F2212/455

  Image or video data · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title