Memory with pattern oriented error correction code

Patent metadata

Field	Value
Publication number	US-10289486-B2
Application number	US-201715649451-A
Country	US
Kind code	B2
Filing date	Jul 13, 2017
Priority date	Jul 13, 2017
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Apparatuses and methods for parity generations in error-correcting code (ECC) memory to reduce chip areas and test time in imaging system are disclosed herein. Memory tests are needed to catch hard failures and soft errors. Random and nondestructive errors are soft errors and are undesirable. Soft errors can be detected and corrected by the disclosed ECC which is based on Hamming code. Before data are written into memory, the first parity generator based on the disclosed ECC generates the first parity by calculating the data. The first parity and data are stored into the ECC memory as a composite word. When the previously stored word is fetched from the ECC memory, the second parity generator based on the disclosed ECC is used to generate the second parity. A comparison between the first and second parity leads to a disclosed error mask, which is used to correct a single bit error if the error only happens to a single bit of the fetched data. A minimum distance of three in the disclosed ECC is maintained to make certain that a single bit is corrected on the read data to retrieve the originally stored memory data.

First claim

What is claimed is:

1. An error-correcting code (ECC) memory, comprising:
a first parity generator configured to receive an input data of m bits and to output a first parity of k bits, wherein each of the k bits of the first parity is a first function of a selected number n of the m bits of the input data, where n and k are both less than m;
a memory array configured to receive the input data and the first parity and, wherein each corresponding bit of the input data and first parity is stored into a memory cell of said memory array and can be accessed as a stored data of m bits and a stored parity of k bits, respectively;
a second parity generator configured to receive the stored data and to output a second parity of k bits, wherein each of the k bits of the second parity is a second function of the selected number n of the m bits of the stored data;
a syndrome generator configured to receive the second parity and the stored parity, and to output an error mask of m bit in response, wherein the syndrome generator performs a bit-by-bit exclusive-OR of the second parity of k bits and the stored parity of k bits, and then outputs the error mask of m bits accordingly; and
a data corrector configured to receive the error mask and the stored data, and to provide an error corrected output data, wherein the error corrected output data is produced by a bit by bit exclusive-OR of the error mask and the stored data.

2. The ECC memory of claim 1 , wherein the first function of the first parity generator is identical to the second function of the second parity generator.

3. The ECC memory of claim 1 , wherein the first function generates each bit of the first parity of k bits to equal each bit of the input data of m bits, wherein every bit of the m bits has the same binary value of zero or one.

4. The ECC memory of claim 1 , wherein the selected number n is an odd integer number.

5. The ECC memory of claim 1 , wherein m, k, and n are each respectively 8, 4 and 5.

6. The ECC memory of claim 5 , wherein for the input 8 bits of the first function consists of d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , and d 8 , and the output 4 bits of the first function consists of p 1 , p 2 , p 3 and p 4 , and wherein
p 1 is an exclusive-OR of d 1 , d 2 , d 4 , d 5 and d 7 ;
p 2 is an exclusive-OR of d 1 , d 3 , d 4 , d 6 and d 7 ;
p 3 is an exclusive-OR of d 2 , d 3 , d 4 , d 5 and d 8 ; and
p 4 is an exclusive-OR of d 3 , d 5 , d 6 , d 7 and d 8 .

7. The ECC memory of claim 6 , wherein a Hamming distance of the first function and the second function is greater than or equal to three.

8. An image memory system, comprising:
a data input buffer configured to receive data input, wherein the data input buffer partitions data input into a plurality of internal data packages and outputs each of the same bit of the plurality of the internal data packages to form a plurality of input data;
a first parity generator configured to receive the input data of m bits and to output a first parity of k bits, wherein each of the k bits of the first parity is produced by a first function of a selected number n of the m bits of the input data, where n and k are both less than m;
a memory array configured to receive the input data and the first parity, wherein the input data and the first parity are stored into said memory array as a stored data and a stored parity, respectively, prior to be fetched by a parity generator, a syndrome generator and a data corrector;
a second parity generator configured to receive the stored data and to output a second parity of k bits, wherein each of the k bits of the second parity is produced by a second function of the selected number n of the m bits of the stored data;
a syndrome generator configured to receive the stored parity and the second parity, and to output an error mask of m bit, wherein each of k bits from both the second parity and the stored parity are compared bit by bit, and decoded to produce the error mask of m bits;
a data corrector configured to receive the error mask and the stored data, and to provide an error corrected output data, wherein the error corrected output data is produced by a bit by bit exclusive-OR of the error mask and the stored data;
a data output buffer configured to receive error corrected output data from the data corrector and to output a data output; and
a display/storage configured to receive the data output.

9. The image memory system of claim 8 , wherein the first function of the first parity generator is identical to the second function of the second parity generator.

10. The image memory system of claim 8 , wherein the first function generates each bit of the first parity of k bits to equal each bit of the input data of m bits, wherein every bit of the m bits has the same binary value, wherein each bit of m-bit input data is set to the same value of 0 or 1.

11. The image memory system of claim 8 , wherein the selected number n is an odd integer number.

12. The image memory system of claim 11 , wherein m, k, and n are each respectively 8, 4 and 5, and wherein for the input 8 bits of the first function consists of d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , and d 8 , and the output 4 bits of the first function consists of p 1 , p 2 , p 3 and p 4 , wherein
p 1 is an exclusive-OR of d 1 , d 2 , d 4 , d 5 and d 7 ;
p 2 is an exclusive-OR of d 1 , d 3 , d 4 , d 6 and d 7 ;
p 3 is an exclusive-OR of d 2 , d 3 , d 4 , d 5 and d 8 ;
p 4 is an exclusive-OR of d 3 , d 5 , d 6 , d 7 and d 8 ; and
a Hamming distance of the first function and the second function is greater than or equal to three.

13. The image memory system of claim 8 , wherein the display/storage is selected from a group consisting of a liquid crystal on silicon display, a LCD display, and a LED display.

14. The image memory system of claim 8 , wherein the display/storage is selected from a group consisting of a nonvolatile memory, a solid state drive, and a hard disk drive.

15. The image memory system of claim 8 , wherein the memory array is a dynamic random access memory (DRAM).

16. A method of generating and using ECC for a memory, comprising:
receiving a data input by a data input buffer, wherein the data input buffer partitions data input into a plurality of internal data packages, and extracts each of a same bit of the plurality of the internal data packages to form a plurality of input data of m bits;
converting the input data to a first parity by a first parity generator, wherein the first parity generator calculates the input data of m bits and outputs the first parity of k bits, wherein each of the k bits of the first parity is a first function of a selected number n of the m bits of the input data, where n and k are both less than m;
storing the input data of m bits and the first parity of k bits to a memory array;
fetching the memory array to acquire a stored data of m bits and a stored parity of k bits;
converting the stored data to a second parity by a second parity generator, wherein the second parity generator converts the stored data of m bits outputs to a second parity of k bits, each of the k bits of the second parity is a second function of the selected number n of the m bits of the stored data;
comparing the stored parity of k bits and the second parity of k bits by a syndrome generator to generate an internal check bits of k bits, wherein the internal check bits of k bits is decoded to generate an error mask of m bits;
comparing the stored data of m bits and the error mask of m bits by a data corrector to generate a plurality of error corrected out

Assignees

• Omnivision Tech Inc

Inventors

• Ryu Hoon
• Na Jong-Sik
• Jung Taehyung

Classifications

• H03M13/2906

  using block codes (H03M13/2957 takes precedence) · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• G11C29/10

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title