Sheet generator for image processor

US10284744B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10284744-B2
Application numberUS-201715598933-A
CountryUS
Kind codeB2
Filing dateMay 18, 2017
Priority dateApr 23, 2015
Publication dateMay 7, 2019
Grant dateMay 7, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.

First claim

Opening claim text (preview).

The invention claimed is: 1. A computing device comprising: one or more stencil processors, wherein each stencil processor is configured to perform one or more kernel functions on stencils of image data using a two-dimensional array of processing elements, wherein each stencil is a two-dimensional region of image data; and a sheet generator comprising a configuration register space and a program memory, wherein the configuration register space is configured to store programmable settings of the sheet generator comprising a line group size, wherein the program memory is configured to store program code that references the programmable settings stored in the configuration register space, wherein the sheet generator is configured to: receive a command to load data from an input line buffer; execute the program code in the program memory to obtain, from the input line buffer, an input line group having a size defined by the line group size of the programmable settings in the configuration register space; execute the program code in the program memory to generate a plurality of initial sheets of image data from the input line group, output the plurality of initial sheets of image data to a first stencil processor of the one or more stencil processors configured to perform one or more kernel functions on stencils of image data of each initial sheet to generate a respective processed sheet of image data, each initial sheet of image data having at least as many pixels as processing elements in the two-dimensional array of processing elements of the first stencil processor, wherein the input line group comprises multiple rows of data from a frame of image data, receive a plurality of processed sheets of image data computed by the two-dimensional array of processing elements of the first stencil processor operating respectively on the plurality of initial sheets of image data, add the processed sheets to an output line group, and write the output line group into an output line buffer of the computing device, the output line group comprising the plurality of processed sheets. 2. The computing device of claim 1 , wherein the computing device comprises a plurality of sheet generators, and wherein each stencil processor of the one or more stencil processors has a respective dedicated sheet generator. 3. The computing device of claim 2 , wherein each sheet generator of the plurality of sheet generators is configured to read from and write to any of a plurality of line buffers of the computing device, the plurality of line buffers including the input line buffer and the output line buffer. 4. The computing device of claim 1 , wherein the sheet generator is configured to obtain, from the input line buffer, first line groups of image data that that are larger than second line groups of image data that the sheet generator is configured to write to one or more output line buffers. 5. The computing device of claim 1 , wherein each initial sheet of image data comprises data of multiple overlapping stencils. 6. The computing device of claim 1 , wherein memory of the first stencil processor comprises a two-dimensional shift-register array. 7. The computing device of claim 1 , wherein each stencil processor has multiple register layers, and wherein the sheet generator is configured to generate separate sheets for each of the multiple register layers and to store each separate sheet in a different register layer of the multiple register layers. 8. The computing device of claim 7 , wherein the sheet generator is configured to generate the separate sheets for each channel of multiple channels of input image data or for each component of multi-dimensional data constructs. 9. The computing device of claim 7 , wherein a bit width of the image data is greater than a bit width of registers of the first stencil processor, wherein the sheet generator is configured to generate a first sheet having a high bit portion of image data and a second sheet having a low bit portion of the image data and to store the first sheet in a first register layer and the second sheet in a second register layer of the first stencil processor. 10. The computing device of claim 1 , wherein the sheet generator is configured to generate an upsampled sheet having upsampled image data by copying multiple instances of each data value in the input line group received from the input line buffer. 11. The computing device of claim 1 , wherein the sheet generator is configured to generate downsampled image data by writing multiple instances of each data value to the output line group provided to the output line buffer. 12. The computing device of claim 1 , wherein the command is issued by a scalar processor of the computing device. 13. The computing device of claim 1 , wherein the programmable settings of the sheet generator further comprise a respective size of a sheet, and wherein each of the plurality of initial sheets of image data has the size defined by the programmable settings. 14. A method comprising: receiving, by a sheet generator, a command to load data from an input line buffer, wherein the sheet generator comprises a configuration register space and a program memory, wherein the configuration register space is configured to store programmable settings of the sheet generator comprising a line group size, wherein the program memory is configured to store program code that references the programmable settings stored in the configuration register space; executing, by the sheet generator, the program code in the program memory to obtain, from the input line buffer, an input line group having a size defined by the line group size of the programmable settings in the configuration register space; executing, by the sheet generator, the program code in the program memory to generate a plurality of initial sheets of image data from the input line group; outputting, by the sheet generator, the plurality of initial sheets of image data from the input line group to a first stencil processor of one or more stencil processors of a computing device, each initial sheet of image data having at least as many pixels as processing elements in a two-dimensional array of processing elements of the first stencil processor, wherein the input line group comprises multiple rows of data from a frame of image data; performing, by the first stencil processor, one or more kernel functions on stencils of image data of each initial sheet of the plurality of initial sheets of image data using the two-dimensional array of processing elements, wherein each stencil is a two-dimensional region of image data; receiving, by the sheet generator, a plurality of processed sheets of image data computed by the two-dimensional array of processing elements of the first stencil processor and adding the processed sheets to an output line group; and writing, by the sheet generator, the output line group into an output line buffer of the computing device, the output line group comprising the plurality of processed sheets. 15. The method of claim 14 , wherein the computing device comprises a plurality of sheet generators, and wherein each stencil processor of the one or more stencil processors has a respective dedicated sheet generator. 16. The method of claim 15 , wherein each sheet generator of the plurality of sheet generators is configured to read from and write to any of a plurality of line buffers of the computing device, the plurality of line buffers including the input line buffer and the output line buffer. 17. The method of claim 14 , wherein the sheet generator is c

Assignees

Inventors

Classifications

  • G06T1/60Primary

    Memory management · CPC title

  • G06T1/20Primary

    Processor architectures; Processor configuration, e.g. pipelining · CPC title

  • for printing sheets · CPC title

  • Display, printing, storage or transmission of additional information, e.g. ID code, date and time or title · CPC title

  • involving image processing hardware · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10284744B2 cover?
A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to…
Who is the assignee on this patent?
Google Llc
What technology area does this patent fall under?
Primary CPC classification G06T1/60. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 07 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).