Adaptive outer code for consistent overprovisioning (OP) level

Patent metadata

Field	Value
Publication number	US-10284231-B2
Application number	US-201715610744-A
Country	US
Kind code	B2
Filing date	Jun 1, 2017
Priority date	Jun 1, 2017
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a solid-state non-volatile memory (NVM) has a total user data storage capacity and an overprovisioning (OP) level. A control circuit writes parity data sets to the NVM each having a plurality of code words and an outer code. The code words include inner codes at an inner code rate to detect and correct read errors in a user data payload. The outer code includes parity data at an outer code rate to detect and correct read errors in the code words. A code adjustment circuit increases the inner code rate to compensate for a measured parameter associated with the NVM, and decreases the outer code rate to maintain the data capacity and OP levels above selected thresholds.

First claim

What is claimed is:

1. An apparatus comprising:
a solid-state non-volatile memory (NVM) having a total user data storage capacity and an overprovisioning (OP) level;
a control circuit configured to write parity data sets to the NVM, each parity data set comprising a plurality of code words and an outer code, each of the plurality of code words comprising a user data payload and an inner code at an inner code rate to detect and correct read errors in the user data payload, the outer code comprising parity data at an outer code rate to detect and correct read errors in the plurality of code words; and
a code adjustment circuit configured to increase the inner code rate of the inner code of at least one parity data set responsive to a measured parameter associated with the NVM, and to decrease the outer code rate of the outer code of the at least one parity data set responsive to the increase of the inner code rate to maintain the total user data storage capacity at or above a first threshold and to maintain the OP level at or above a second threshold.

2. The apparatus of claim 1 , wherein the code adjustment circuit increases the inner code rate by increasing a size of the inner code in terms of a total number of bits stored to the NVM for an associated code word.

3. The apparatus of claim 1 , wherein the code adjustment circuit decreases the outer code rate by increasing a total number of the code words protected by the outer code in the at least one parity data set so that a ratio between a total number of bits stored to the NVM for the outer code and a total number of bits stored to the NVM for the total number of the code words protected by the outer code is decreased.

4. The apparatus of claim 1 , wherein each code word has a fixed size comprising a first number of bits corresponding to the user data payload and a second number of bits corresponding to the inner code, and wherein the code adjustment circuit increases the inner code rate by increasing the first number of bits and decreasing the second number of bits in each code word.

5. The apparatus of claim 1 , wherein the NVM is an erasable memory, and the OP level comprises additional free space within the erasable memory that is maintained to facilitate garbage collection operations upon the NVM.

6. The apparatus of claim 5 , wherein the first threshold represents a minimum data storage capacity communicated to a user of the NVM.

7. The apparatus of claim 1 , wherein the inner code comprises LDPC (low density parity check) code bits used by an LDPC decoder to correct bit errors in the associated user data payload.

8. The apparatus of claim 1 , wherein an integer number of the code words are written to each of a plurality of pages in the NVM, each page is stored across a set of solid-state memory cells in the NVM connected to a common word line, and the outer code in a selected parity data set protects the code words written to a plurality of pages.

9. The apparatus of claim 8 , wherein the outer code occupies an additional page of the selected parity data set.

10. The apparatus of claim 8 , wherein the code adjustment circuit provides a first outer code rate for a first parity data set in which the outer code protects a first integer number of pages, and wherein the code adjustment circuit reduces the first outer code rate to provide a second outer code rate for a second parity data set in which the outer code protects a second integer number of pages greater than the first integer number of pages.

11. The apparatus of claim 1 , wherein the NVM comprises a flash memory having a plural number N dies each concurrently accessible using parallel data transfer lanes, wherein a selected parity data set comprises code words written to N−1 of the dies and the outer code written to the remaining one of the dies.

12. The apparatus of claim 1 , wherein the NVM is a NAND flash memory, the control circuit is a device management module (DMM) circuit, and the code adjustment circuit forms a portion of a programmable processor of a controller coupled to the DMM circuit.

13. A method comprising:
writing a first parity data set to a non-volatile memory (NVM) comprising a plurality of code words and an outer code, each of the plurality of code words comprising a user data payload and an inner code at a first inner code rate to detect and correct read errors in the user data payload, the outer code comprising parity data at a first outer code rate to detect and correct read errors in the plurality of code words;
measuring a parameter associated with the NVM; and
subsequently writing a second parity data set to the NVM having a second inner code rate greater than the first inner code rate responsive to the measured parameter associated with the NVM and a second outer code rate less than the first outer code rate to maintain a total user data storage capacity of the NVM at or above a first threshold and to maintain an overprovisioning (OP) level of the NVM at or above a second threshold.

14. The method of claim 13 , wherein the first inner code rate provides a first inner code in the first parity data set with a first total number of bits, and the second inner code rate provides a second inner code in the second parity data set with a second total number of bits greater than the first total number of bits.

15. The method of claim 13 , wherein the first outer code rate corresponds to a first total number of the code words in the first parity data set, and the second outer code rate corresponds to a greater, second total number of the code words in the second parity data set.

16. The method of claim 13 , wherein each code word has a fixed size comprising a first number of bits corresponding to the user data payload and a second number of bits corresponding to the inner code, and wherein the inner code rate is increased by increasing the first number of bits and decreasing the second number of bits in each code word.

17. The method of claim 13 , wherein the NVM is an erasable memory, and the OP level comprises additional free space within the erasable memory that is maintained to facilitate garbage collection operations upon the NVM.

18. The method of claim 13 , wherein the inner code comprises LDPC (low density parity check) code bits used by an LDPC decoder to correct bit errors in the associated user data payload.

19. The method of claim 13 , wherein an integer number of the code words are written to each of a plurality of pages in the NVM, each page is stored across a set of solid-state memory cells in the NVM connected to a common word line, and the outer code in a selected parity data set protects the code words written to a plurality of pages.

20. The method of claim 13 , wherein the NVM is a NAND flash memory.

Assignees

• Seagate Technology Llc

Inventors

• Canepa Timothy

Classifications

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title