Amplifier die with elongated side pads, and amplifier modules that incorporate such amplifier die

Patent metadata

Field	Value
Publication number	US-10284146-B2
Application number	US-201615366550-A
Country	US
Kind code	B2
Filing date	Dec 1, 2016
Priority date	Dec 1, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

An embodiment of a Doherty amplifier module includes a substrate, a first amplifier die, and a second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. The first and second amplifier die each also include an elongated output pad that is configured to enable a pluralities of wirebonds to be connected in parallel along the length of the elongated output pad so that the pluralities of wirebonds extend in perpendicular directions to the first and second signal paths.

First claim

What is claimed is:

1. A monolithic power transistor integrated circuit (IC) comprising:
a semiconductor die having a top surface, a bottom surface, parallel first and second sides extending between the top and bottom surfaces, and parallel third and fourth sides extending between the first and second sides and between the top and bottom surfaces;
a transistor integrated within the semiconductor die, wherein the transistor includes a control terminal and a current conducting terminal;
an input terminal electrically coupled to the control terminal of the transistor; and
an output terminal electrically coupled to the current conducting terminal of the transistor, wherein a direction of a signal path through the power transistor IC extends from the first side of the semiconductor die toward the second side, the output terminal has an elongated first pad that is proximate to the third side of the semiconductor die, the elongated first pad has a first length that extends in parallel with the third side of the semiconductor die, the elongated first pad is positioned between the transistor and the third side of the semiconductor die, and the elongated first pad is configured to enable a first plurality of wirebonds to be connected in parallel along the first length of the elongated first pad.

2. The power transistor IC of claim 1 , wherein:
the first length is in a range between 200 microns and 400 microns.

3. A monolithic power transistor integrated circuit (IC) comprising:
a semiconductor die having a top surface, a bottom surface, parallel first and second sides extending between the top and bottom surfaces, and parallel third and fourth sides extending between the first and second sides and between the top and bottom surfaces;
one or more transistors integrated within the semiconductor die, wherein the one or more transistors include a control terminal and a current conducting terminal;
an input terminal electrically coupled to the control terminal of the one or more transistors; and
an output terminal electrically coupled to the current conducting terminal of the one or more transistors, wherein a direction of a signal path through the power transistor IC extends from the first side of the semiconductor die toward the second side, and the output terminal includes
an elongated first pad that is proximate to the third side of the semiconductor die, the elongated first pad has a first length that extends in parallel with the third side of the semiconductor die, and the elongated first pad is configured to enable a first plurality of wirebonds to be connected in parallel along the first length of the elongated first pad, and
an elongated second pad that is electrically coupled to the elongated first pad, wherein the elongated second pad is proximate to the second side of the semiconductor die, and the elongated second pad has a second length that extends in parallel with the second side of the semiconductor die, and the elongated second pad is configured to enable a second plurality of wirebonds to be connected in parallel along the second length of the elongated second pad.

4. The power transistor IC of claim 3 , wherein:
the first length is configured to enable the first plurality of wirebonds to be connected in parallel along the first length of the elongated first pad so that the each of the wirebonds in the first plurality of wirebonds extend in a perpendicular direction from the third side of the semiconductor die; and
the second length is configured to enable the second plurality of wirebonds to be connected in parallel along the second length of the elongated second pad so that the each of the wirebonds in the second plurality of wirebonds extend in a perpendicular direction from the second side of the semiconductor die.

5. The power transistor IC of claim 3 , wherein:
the first length is in a range between 200 microns and 400 microns; and
the second length is in a range between 800 microns and 1800 microns.

6. The power transistor IC of claim 3 , wherein the output terminal further comprises:
an elongated third pad that is electrically coupled to the elongated first pad and to the elongated second pad, wherein the elongated third pad is proximate to the fourth side of the semiconductor die, the elongated third pad has a third length that extends in parallel with the fourth side of the semiconductor die, and the elongated third pad is configured to enable a third plurality of wirebonds to be connected in parallel along the third length of the elongated third pad.

7. The power transistor IC of claim 6 , wherein:
the first length is configured to enable the first plurality of wirebonds to be connected in parallel along the first length of the elongated first pad so that the each of the wirebonds in the first plurality of wirebonds extend in a perpendicular direction from the third side of the semiconductor die;
the second length is configured to enable the second plurality of wirebonds to be connected in parallel along the second length of the elongated second pad so that the each of the wirebonds in the second plurality of wirebonds extend in a perpendicular direction from the second side of the semiconductor die; and
the third length is configured to enable the third plurality of wirebonds to be connected in parallel along the third length of the elongated third pad so that the each of the wirebonds in the third plurality of wirebonds extend in a perpendicular direction from the fourth side of the semiconductor die.

8. A monolithic power transistor integrated circuit (IC) comprising:
a semiconductor die that includes
a top surface,
a bottom surface,
parallel first and second sides extending between the top and bottom surfaces,
parallel third and fourth sides extending between the first and second sides and between the top and bottom surfaces,
a semiconductor substrate with a top surface and a bottom surface, wherein the bottom surface of the semiconductor substrate defines the bottom surface of the semiconductor die, and
a plurality of patterned conductive layers formed over the top surface of the semiconductor substrate;

one or more transistors integrated within the semiconductor die, wherein the one or more transistors include a control terminal and a current conducting terminal, and wherein the current conducting terminal is coupled to a doped semiconductor region proximate to the top surface of the semiconductor substrate;
an input terminal electrically coupled to the control terminal of the one or more transistors; and
an output terminal electrically coupled to the current conducting terminal of the one or more transistors, wherein a direction of a signal path through the power transistor IC extends from the first side of the semiconductor die toward the second side, the output terminal has an elongated first pad that is proximate to the third side of the semiconductor die, the elongated first pad has a first length that extends in parallel with the third side of the semiconductor die, the elongated first pad is configured to enable a first plurality of wirebonds to be connected in parallel along the first length of the elongated first pad, and the elongated first pad is formed from a portion of a patterned conductive layer that is closest to the top surface of the semiconductor die.

9. The power transistor IC of claim 1 , wherein the semiconductor die comprises:
a semiconductor substrate with a top surface and a bottom surface, wherein the bottom surface of the semiconductor substrate defines the bottom surface of the semiconductor die, and the current conducting terminal includes a doped semiconductor region proximate to the top surface of the semiconductor substrate; and
a plurality of patter

Assignees

• Nxp Usa Inc

Inventors

• Wu Yu-Ting
• Yang Nick
• Schultz Joseph Gerard

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title