Amplifier devices with in-package transmission line combiner

Patent metadata

Field	Value
Publication number	US-9621115-B1
Application number	US-201514966922-A
Country	US
Kind code	B1
Filing date	Dec 11, 2015
Priority date	Dec 11, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. The amplifiers described herein use a combiner that is implemented inside the device package. Specifically, the amplifiers can be implemented with a combiner that includes a transmission line inside the device package, where the transmission line has a length between first and second ends configured to provide an impedance inverter between the outputs (e.g., drain terminals) of transistors in the amplifier.

First claim

What is claimed is:

1. An amplifier comprising:
a device package including an output lead and at least one input lead, the device package encasing:
a first amplifier with a first transistor including a first transistor output;
a second amplifier with a second transistor including a second transistor output; and
a combiner coupled to the first transistor output and the second transistor output, the combiner including a transmission line having a length configured to provide at least a portion of an impedance inverter between the first transistor output and the second transistor output, wherein the impedance inverter is configured to compensate for a first transistor parasitic capacitance and a second transistor parasitic capacitance, and wherein the impedance inverter further includes a first set of bond wires and a second set of bond wires.

2. The amplifier of claim 1 , wherein the combiner is coupled to the first transistor output through the first set of bond wires coupled to a first end of the transmission line and wherein the combiner is coupled to the second transistor output through the second set of bond wires coupled to a second end the transmission line.

3. The amplifier of claim 2 , further comprising a third set of bond wires coupling the second transistor output to the output lead.

4. The amplifier of claim 1 , wherein the amplifier comprises a Doherty amplifier, and wherein the first amplifier comprises a carrier amplifier and wherein the second amplifier comprises a peaking amplifier in the Doherty amplifier.

5. The amplifier of claim 1 , wherein the transmission line comprises a conductor defined on a printed circuit board (PCB).

6. The amplifier of claim 1 , wherein the transmission line comprises a conductive feature of an integrated passive device (IPD).

7. The amplifier of claim 1 , wherein the transmission line comprises a microstrip line.

8. The amplifier of claim 1 , wherein the transmission line is formed on a substrate distinct from a die on which either the first transistor is formed, the second transistor is formed, or both the first and second transistor is formed.

9. The amplifier of claim 1 , wherein the transmission line has a length between 0.5 to 0.9 of a ¼ wavelength of a radio frequency (RF) signal at a center operational frequency of the amplifier.

10. The amplifier of claim 1 , further comprising a biasing circuit, the biasing circuit coupled to both the first transistor output and the second transistor output to provide a shared bias voltage to the first transistor and the second transistor.

11. An amplifier comprising:
a device package including an output lead and at least one input lead, the device package encasing:
a carrier amplifier, the carrier amplifier including a carrier transistor with a carrier transistor parasitic capacitance and a carrier transistor output;
a peaking amplifier, the peaking amplifier including a peaking transistor with a peaking transistor parasitic capacitance and a peaking transistor output; and
a combiner, the combiner comprising a first set of bond wires, a second set of bond wires, and a transmission line, wherein the first set of bond wires couples the carrier transistor output to a first end of the transmission line, and the second set of bond wires couples the peaking transistor output to a second end of the transmission line, and wherein the transmission line has a length between the first end and the second end configured to provide, in combination with the carrier transistor parasitic capacitance, the peaking transistor parasitic capacitance, the first set of bond wires and the second set of bond wires, an impedance inverter between the carrier transistor output and the peaking transistor output.

12. The amplifier of claim 11 , further comprising a third set of bond wires coupling the peaking transistor output to the output lead.

13. The amplifier of claim 11 , wherein the transmission line comprises a conductor defined on a printed circuit board (PCB).

14. The amplifier of claim 11 , wherein the transmission line comprises a conductive feature of an integrated passive device (IPD).

15. The amplifier of claim 11 , wherein the transmission line comprises a microstrip line.

16. The amplifier of claim 11 , wherein the transmission line is formed on a substrate distinct from a die on which either the carrier transistor is formed, the peaking transistor is formed, or both the carrier and peaking transistor are formed.

17. The amplifier of claim 11 , further comprising a biasing circuit, the biasing circuit coupled to both a drain of the carrier transistor and a drain of the peaking transistor to provide a shared bias voltage to the carrier transistor and the peaking transistor.

18. The amplifier of claim 11 , wherein the transmission line has a length between 0.5 to 0.9 of a ¼ wavelength of an RF signal at a center operational frequency of the amplifier.

19. A Doherty amplifier, comprising:
a device package including an output lead and at least one input lead, the device package encasing:
a carrier transistor including a carrier transistor parasitic capacitance and a carrier transistor output;
a peaking transistor including a peaking transistor parasitic capacitance and a peaking transistor output;
a transmission line having a length, the transmission line formed on a substrate distinct from a die on which the carrier transistor is formed, the peaking transistor is formed, or both the carrier and peaking transistors are formed;
a first set of bond wires coupling the carrier transistor output to a first end of the transmission line;
a second set of bond wires coupling the peaking transistor output to a second end of the transmission line;
a third set of bond wires coupling the peaking transistor output to the output lead; and
wherein a transmission line length between the first and second ends is configured to provide an impedance inverter between the carrier transistor output and the peaking transistor output in combination with the carrier transistor parasitic capacitance, the peaking transistor parasitic capacitance, the first set of bond wires and the second set of bond wires.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Wu Yu-Ting D

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H03F1/0288 Primary

  using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title