Modulated super junction power MOSFET devices

Patent metadata

Field	Value
Publication number	US-10283587-B2
Application number	US-201815889784-A
Country	US
Kind code	B2
Filing date	Feb 6, 2018
Priority date	Jun 23, 2014
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.

First claim

What is claimed is:

1. A super junction power metal oxide semiconductor field effect transistor (MOSFET) device having a channel of first type dopant, said device comprising:
a plurality of columns, wherein said plurality of columns comprises:
a first plurality of columns comprising second type dopant that is different from said first type dopant, said first plurality of columns formed in a region comprising said first type dopant, each column in said first plurality of columns having substantially a same first width; and
a second plurality of columns comprising said second type dopant, said second plurality of columns formed in said region comprising said first type dopant, each column in said second plurality of columns having substantially a same second width;

wherein said first width is different from said second width, and wherein said second plurality of columns comprises columns that are surrounded by columns of said first plurality of columns, and wherein each column in said first plurality of columns is electrically and physically in contact with a respective base region of said second type dopant that is electrically and physically in contact with a respective contact region of said second type dopant that is physically and electrically in contact with source metal, and wherein each column in said second plurality of columns is electrically and physically in contact with a respective base region of said second type dopant that is electrically and physically in contact with a respective contact region of said second type dopant that is physically and electrically in contact with said source metal.

2. The super junction power MOSFET device of claim 1 wherein an average value of said first width across said first plurality of columns is greater than an average value of said second width across said second plurality of columns.

3. The super junction power MOSFET device of claim 1 wherein said first plurality of columns comprises a first column having a first cross-section that has a first shape and wherein said second plurality of columns comprises a second column having a second cross-section that has a second shape that is different from said first shape, said first cross-section orthogonal to an axis of said first column and said second cross-section orthogonal to an axis of said second column.

4. The super junction power MOSFET device of claim 3 wherein said first shape and said second shape are selected from the group consisting of: a circular shape; a squarish shape; and a hexagonal shape.

5. The super junction power MOSFET device of claim 1 wherein said first plurality of columns and said second plurality of columns are at an active region of said device but are outside termination regions of said device.

6. The super junction power MOSFET device of claim 1 wherein each column in said first plurality of columns has substantially a same first width along its entire length below its said respective base region, and wherein each column in said second plurality of columns has substantially a same second width along its entire length below its said respective base region.

7. A semiconductor device comprising:
a substrate comprising a first type dopant;
a super junction structure coupled to said substrate and comprising a plurality of columnar regions, said plurality of columnar regions comprising a first plurality of columnar first regions formed in a third region and a second plurality of columnar second regions formed in said third region, said third region comprising said first type dopant, said columnar first regions and said columnar second regions each comprising second type dopant that is different from said first type dopant, wherein each of said columnar first regions has a first width measured orthogonal to the longitudinal axis of said first region, and wherein each of said columnar second regions has a second width measured orthogonal to the longitudinal axis of said second region, said first width different from said second width;
wherein said second plurality of columnar second regions comprises columnar regions that are surrounded by columnar regions of said first plurality of columnar first regions, and wherein each columnar region of said first plurality of columnar first regions is electrically and physically in contact with a respective base region of said second type dopant that is electrically and physically in contact with a respective contact region of said second type dopant that is physically and electrically in contact with source metal, and wherein each columnar region of said second plurality of columnar second regions is electrically and physically in contact with a respective base region of said second type dopant that is electrically and physically in contact with a respective contact region of said second type dopant that is physically and electrically in contact with said source metal.

8. The semiconductor device of claim 7 wherein an average value of said first width across said first plurality of columnar first regions is greater than an average value of said second width across said second plurality of columnar second regions.

9. The semiconductor device of claim 7 wherein each columnar region in said first plurality of columnar first regions has a first cross-section that has a first shape and wherein each columnar region in said second plurality of columnar second regions has a second cross-section that has a second shape that is different from said first shape, said first cross-section orthogonal to axes of said columnar first regions and said second cross-section orthogonal to axes of said columnar second regions.

10. The semiconductor device of claim 9 wherein said first shape and said second shape are selected from the group consisting of: a circular shape; a squarish shape; and a hexagonal shape.

11. The semiconductor device of claim 7 wherein said first plurality of columnar first regions and said second plurality of columnar second regions are at an active region of said device but are outside termination regions of said device.

12. The semiconductor device of claim 7 wherein each of said columnar first regions has substantially a same first width along its entire length below its said respective base region, the first width measured orthogonal to the longitudinal axis of said columnar first regions, wherein each of said columnar second regions has substantially a same second width along its entire length below its said respective base region, the second width measured orthogonal to the longitudinal axis of said columnar second regions, and wherein said first width is different from said second width.

13. A semiconductor device comprising a gate, source, and drain, said semiconductor device comprising:
a substrate of said first type dopant; and
an epitaxial layer coupled to said substrate, said epitaxial layer doped with said first type dopant, said epitaxial layer having formed therein a plurality of columns, wherein said plurality of columns comprises:
a first plurality of columns comprising second type dopant that is different from said first type dopant, each column in said first plurality of columns having substantially a same first width; and
a second plurality of columns comprising said second type dopant, each column in said second plurality of columns having substantially a same second width;
wherein said first width is different from said second width, and wherein said second plurality of columns comprises columns that are surrounded by columns of said first plurality of columns, and wherein each column in said first plurality of columns is electrically and physically in contact with a respect

Assignees

• Vishay Siliconix

Inventors

• Pattanayak Deva
• Tornblad Olof

Classifications

• H01L29/0634 Primary

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/7802

  Electricity · mapped topic

• H01L29/0696

  Electricity · mapped topic

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title