Methods and apparatus for three-dimensional nonvolatile memory

Patent metadata

Field	Value
Publication number	US-10283567-B2
Application number	US-201715441284-A
Country	US
Kind code	B2
Filing date	Feb 24, 2017
Priority date	Feb 24, 2017
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.

First claim

The invention claimed is:

1. A method comprising:
forming a word line above a substrate, the word line disposed in a first direction;
forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction;
forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material comprising a semiconductor material layer and a conductive oxide material layer;
forming a first barrier material layer between the word line and the nonvolatile memory material;
forming a second barrier material layer between the bit line and the nonvolatile memory material;
forming a memory cell comprising the nonvolatile memory material at an intersection of the bit line and the word line;
forming a global bit line above the substrate, the global bit line disposed in a third direction perpendicular to the first direction and the second direction; and
forming a transistor between the bit line and the global bit line.

2. The method of claim 1 , further comprising forming an intermediate barrier material layer between the semiconductor material layer and the conductive oxide material layer.

3. The method of claim 1 , wherein the first barrier material layer and the second barrier material layer comprise one or more of aluminum oxide, zirconium oxide, hafnium oxide, TaO, AlHfO, and AlZrO.

4. The method of claim 1 , wherein the first barrier material layer and the second barrier material layer each comprise a thickness of between about 0.3 nm and about 1.5 nm.

5. The method of claim 1 , wherein:
the semiconductor material layer comprises one or more of amorphous silicon, amorphous germanium, amorphous selenium, amorphous silicon-germanium, amorphous tantalum nitride, and amorphous tantalum silicon nitride; and
the conductive oxide material layer comprises one or more of crystalline titanium oxide, crystalline zinc oxide, crystalline tungsten oxide, crystalline strontium titanate, yttria-stabilized zirconia and crystalline praseodymium calcium manganese oxide.

6. The method of claim 1 , wherein the bit line comprises one or more of titanium nitride, tantalum nitride, tantalum carbide, and titanium carbide.

7. The method of claim 1 , further comprising:
forming a plurality of word lines above the substrate, each of the word lines disposed in the first direction;
forming the nonvolatile memory material between the bit line and each of the plurality of word lines;
forming the first barrier material layer between the nonvolatile memory material and each of the plurality of word lines; and
forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the bit line and a corresponding one of the word lines.

8. The method of claim 1 , further comprising:
forming a plurality of bit lines above the substrate, each of the bit lines disposed in the second direction;
forming the nonvolatile memory material between the word line and each of the plurality of bit lines;
forming the second barrier material layer between the nonvolatile memory material and each of the plurality of bit lines; and
forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the word line and a corresponding one of the bit lines.

9. The method of claim 1 , wherein the transistor comprises a vertically-oriented transistor.

10. A method comprising:
forming a word line layer above a substrate, the word line layer disposed in a first direction;
forming a dielectric material above a substrate;
forming a hole in the dielectric material, the hole disposed in a second direction perpendicular to the first direction;
forming a first barrier material layer on a sidewall of the hole and adjacent the word line layer;
forming a nonvolatile memory material on the first barrier material layer, the nonvolatile memory material comprising a semiconductor material layer and a conductive oxide material layer;
forming a second barrier material layer on the nonvolatile memory material;
forming a bit line in the hole and adjacent the second barrier material layer; and
forming a memory cell comprising the nonvolatile memory material at an intersection of the bit line and the word line layer.

11. The method of claim 10 , further comprising forming an intermediate barrier material layer between the semiconductor material layer and the conductive oxide material layer.

12. The method of claim 10 , wherein the first barrier material layer and the second barrier material layer comprise one or more of aluminum oxide, zirconium oxide, hafnium oxide, TaO, AlHfO, and AlZrO.

13. The method of claim 10 , wherein the first barrier material layer and the second barrier material layer each comprise a thickness of between about 0.3 nm and about 1.5 nm.

14. The method of claim 10 , wherein:
the semiconductor material layer comprises one or more of amorphous silicon, amorphous germanium, amorphous selenium, amorphous silicon-germanium, amorphous tantalum nitride, and amorphous tantalum silicon nitride; and
the conductive oxide material layer comprises one or more of crystalline titanium oxide, crystalline zinc oxide, crystalline tungsten oxide, crystalline strontium titanate, yttria-stabilized zirconia and crystalline praseodymium calcium manganese oxide.

15. The method of claim 10 , wherein the bit line comprises one or more of titanium nitride, tantalum nitride, tantalum carbide, and titanium carbide.

16. The method of claim 10 , further comprising:
forming a plurality of word line layers above the substrate, each of the word line layers disposed in the first direction;
forming the first barrier material layer between the nonvolatile memory material and each of the plurality of word lines; and
forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the bit line and a corresponding one of the word line layers.

17. The method of claim 10 , further comprising:
forming a plurality of holes in the dielectric material, each of the plurality of holes disposed in the second direction;
forming the first barrier material layer on a sidewall of each of the holes and adjacent the word line layer;
forming a nonvolatile memory material on each of the first barrier material layers, the nonvolatile memory material comprising a semiconductor material layer and a conductive oxide material layer;
forming a second barrier material layer on each nonvolatile memory material;
forming a plurality of bit lines, each bit line disposed in a corresponding one of the holes and adjacent the second barrier material layer; and
forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the word line layer and a corresponding one of the bit lines.

18. A method of forming a monolithic three-dimensional memory array, the method comprising:
forming a stack of conductive material layers above a substrate;
etching the stack of conductive material layers to form a row of conductive material layers;
forming a dielectric material adjacent the row of conductive material layers;
forming a hole in the dielectric material, the hole disposed adjacent the row of conductive material layers;
forming on a sidewall of the hole a first barrier material layer, a nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, and a secon

Assignees

• Sandisk Technologies Llc

Inventors

• Saenz Juan
• Kamalanathan Deepak
• Zhou Guangle
• Wu Ming-Che
• Kumar Tanmay

Classifications

• H01L45/1233

  Electricity · mapped topic

• H01L45/14

  Electricity · mapped topic

• H01L27/249 Primary

  Electricity · mapped topic

• H01L45/10

  Electricity · mapped topic

• H01L45/1683

  Electricity · mapped topic