Pixel circuit

Patent metadata

Field	Value
Publication number	US-10283559-B2
Application number	US-201715640968-A
Country	US
Kind code	B2
Filing date	Jul 3, 2017
Priority date	Aug 9, 2013
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.

First claim

What is claimed is:

1. A pixel arrangement, comprising:
a photodiode;
a transfer gate transistor configured to transfer charge from the photodiode to a sense node, said transfer gate transistor having a control terminal configured to be controlled by a transfer gate signal;
a reset transistor configured to reset the sense node in response to a reset signal; and
a source follower transistor controlled by a voltage on the sense node;
wherein the transfer gate signal, during a read operation, has a transfer gate voltage that transitions from a first voltage level for controlling the transfer gate transistor to be turned off to a second voltage level and stays at that second voltage level for a first time period causing a voltage of said sense node to increase without turning on said transfer gate transistor to transfer charge from the photodiode to the sense node, and then the transfer gate voltage further transitions, after the first time period, from the second voltage level to a third voltage level for controlling the transfer gate transistor to be turned on and stays at that third voltage level for a second time period causing the transfer gate transistor to transfer charge from the photodiode to the sense node; and
wherein the second voltage level is between the first and third voltage levels.

2. The pixel arrangement of claim 1 , wherein the source follower outputs the voltage at the sense node while the transfer gate voltage is at the second voltage level as a first sampled voltage and wherein the source follower outputs the voltage at the sense node after the transfer gate voltage is at the third voltage level as a second sampled voltage.

3. The pixel arrangement of claim 2 , further comprising a read transistor coupled between the source follower transistor and an output, wherein said read transistor is controlled to turn on to pass the first sampled voltage for output and to pass the second sampled voltage for output.

4. The pixel arrangement of claim 2 , wherein said transfer gate voltage further transitions, after the second time period, from the third voltage level to a fourth voltage level and stays at said fourth voltage level for a third time period during which the second sampled voltage is output, and then transitions, after the third time period, from the fourth voltage level to the first voltage level, and wherein the fourth voltage level is between the first and second voltage levels.

5. The pixel arrangement of claim 2 , wherein said reset signal is pulsed at a beginning of said read operation.

6. The pixel arrangement of claim 2 , wherein said reset signal is pulsed while the first and second sampled voltages are output.

7. The pixel arrangement of claim 1 , wherein the pixel arrangement is implemented as an integrated circuit.

8. The pixel arrangement of claim 1 , further comprising:
a further photodiode;
a further transfer gate transistor configured to transfer charge from the further photodiode to a sense node, said further transfer gate transistor having a control terminal configured to be controlled by a further transfer gate signal;
wherein each of said transfer gate signal and said further transfer gate signal have said transfer gate voltage.

9. A pixel arrangement, comprising:
a first photodiode;
a second photodiode;
a first transfer gate transistor configured to transfer charge from the first photodiode to a sense node, said first transfer gate transistor having a control terminal configured to be controlled by a first transfer gate signal;
a second transfer gate transistor configured to transfer charge from the second photodiode to a sense node, said second transfer gate transistor having a control terminal configured to be controlled by a second transfer gate signal;
a reset transistor configured to reset the sense node in response to a reset signal; and
a source follower transistor controlled by a voltage on the sense node;
wherein each of the first and second transfer gate signals, during a read operation, has a transfer gate voltage that transitions from a first voltage level for controlling the first or second transfer gate transistor to be turned off to a second voltage level and stays at that second voltage level for a first time period causing a voltage of said sense node to increase without turning on said first or second transfer gate transistor to transfer charge from the corresponding first or second photodiode to the sense node, and then the transfer gate voltage further transitions, after the first time period, from the second voltage level to a third voltage level for controlling the first or second transfer gate transistor to be turned on and stays at that third voltage level for a second time period causing the first or second transfer gate transistor to transfer charge from the corresponding first or second photodiode to the sense node; and
wherein the second voltage level is between the first and third voltage levels.

10. The pixel arrangement of claim 9 , wherein the source follower outputs the voltage at the sense node while the transfer gate voltage is at the second voltage level as a first sampled voltage and wherein the source follower outputs the voltage at the sense node after the transfer gate voltage is at the third voltage level as a second sampled voltage.

11. The pixel arrangement of claim 10 , further comprising a read transistor coupled between the source follower transistor and an output, wherein said read transistor is controlled to turn on to pass the first sampled voltage for output and to pass the second sampled voltage for output.

12. The pixel arrangement of claim 10 , wherein said transfer gate voltage further transitions, after the second time period, from the third voltage level to a fourth voltage level and stays at said fourth voltage level for a third time period during which the second sampled voltage is output, and then transitions, after the third time period, from the fourth voltage level to the first voltage level, and wherein the fourth voltage level is between the first and second voltage levels.

13. The pixel arrangement of claim 10 , wherein said reset signal is pulsed at a beginning of said read operation.

14. The pixel arrangement of claim 10 , wherein said reset signal is pulsed while the first and second sampled voltages are output.

15. The pixel arrangement of claim 9 , wherein the pixel arrangement is implemented as an integrated circuit.

Assignees

• St Microelectronics Grenoble 2
• St Microelectronics Res & Dev Ltd

Inventors

• Storm Graeme
• Mandier Christophe

Classifications

• H04N25/57

  Control of the dynamic range · CPC title

• H04N25/626

  Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title