Stacked image sensor having a barrier layer

Patent metadata

Field	Value
Publication number	US-10283547-B2
Application number	US-201615395071-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Mar 28, 2014
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.

First claim

What is claimed is:

1. An image sensor, comprising:
a first device that includes:
a first substrate;
a first interconnect structure that includes a plurality of first metal lines;
a first isolation layer, wherein the first metal lines are disposed between the first substrate and the first isolation layer;

a second device that includes:
a second substrate;
a second interconnect structure that includes a plurality of second metal lines;
a second isolation layer, wherein the second metal lines are disposed between the second substrate and the second isolation layer;

wherein:
the first device and the second device are bonded together through a bonding interface;
a first structure in the first substrate is at least partially located over one of the first metal lines;
a second structure in the first substrate extends through the bonding interface and is at least partially located over one of the second metal lines; and
a continuous conductive element is disposed in both the first structure and the second structure and is electrically coupled to both the one of the first metal lines and the one of the second metal lines, wherein a first portion of the conductive element disposed in the first structure defines a first U-shaped structure, and a second portion of the conductive element disposed in the second structure defines a second U-shaped structure, and wherein a bottom surface of the second U-shaped structure is in direct contact with an upper surface of the one of the second metal lines.

2. The image sensor of claim 1 , wherein the first isolation layer and the second isolation layer each contain silicon nitride.

3. The image sensor of claim 1 , wherein the continuous conductive element is separated from the first substrate by a dielectric material.

4. The image sensor of claim 1 , wherein the second device includes an Application Specific Integrated Circuit (ASIC).

5. The image sensor of claim 1 , wherein the continuous conductive element does not completely fill the second structure.

6. The image sensor of claim 1 , wherein the first device further comprises a first dielectric layer.

7. The image sensor of claim 6 , wherein the first isolation layer and the first dielectric layer have different material compositions.

8. The image sensor of claim 1 , wherein the second device further comprises a second dielectric layer.

9. The image sensor of claim 8 , wherein the second isolation layer and the second dielectric layer have different material compositions.

10. The image sensor of claim 1 , wherein the first device further includes a light-sensing element disposed in the first substrate.

11. The image sensor of claim 10 , wherein:
the first interconnect structure is disposed on a first side of the first substrate; and
the light-sensing element is configured to sense light that enters the first substrate through a second side opposite the first side.

12. The image sensor of claim 10 , wherein:
the light-sensing element is disposed in a pixel region of the image sensor; and
the continuous conductive element is disposed in a periphery region of the image sensor that is different from the pixel region.

13. The image sensor of claim 12 , wherein the image sensor further comprises a bonding pad region and a scribe line region, the bonding pad region and the scribe line region being different than the pixel region and the periphery region.

14. An image sensor, comprising:
a sensor portion that includes:
a first substrate having a first side and a second side opposite the first side;
a radiation-sensing region formed in the first substrate, the radiation-sensing region being configured to detect radiation that enters the first substrate through the second side;
a first interconnect structure disposed over the first side of the first substrate, the first interconnect structure including one or more first metal lines;
a first isolation layer disposed over the first interconnect structure; and
a first dielectric layer disposed over the first isolation layer such that the first isolation layer is disposed between the first interconnect structure and the first dielectric layer, wherein the first isolation layer and the first dielectric layer have different material compositions;

an Application Specific Integrated Circuit (ASIC) portion that includes:
a second substrate;
a second interconnect structure disposed over the second substrate, the second interconnect structure including one or more second metal lines;
a second isolation layer disposed over the second interconnect structure; and
a second dielectric layer disposed over the second isolation layer such that the second isolation layer is disposed between the second interconnect structure and the second dielectric layer, wherein the second isolation layer and the second dielectric layer have different material compositions;

wherein:
the sensor portion and the ASIC portion are bonded together at least in part through the first dielectric layer and the second dielectric layer;
a first structure extends partially through the first substrate and is partially located over one of the first metal lines;
a second structure extends completely through the first substrate, the first interconnect structure, the first isolation layer, the first dielectric layer, the second dielectric layer, and the second isolation layer, wherein the second structure is partially located over one of the second metal lines; and
a continuous conductive layer is disposed in the first structure and in the second structure, wherein the continuous conductive layer electrically interconnects the first metal line located under the first structure to the second metal line located under the second structure, wherein a portion of the conductive layer disposed in the second structure includes side segments and a bottom segment connecting the side segments, wherein the side segments are disposed on sidewalls of at least the first and second isolation layers and the first and second dielectric layers, and wherein the bottom segment is disposed on the one of the second metal lines.

15. The image sensor of claim 14 , wherein:
the first dielectric layer and the second dielectric layer each contain silicon oxide; and
the first isolation layer and the second isolation layer each contain silicon nitride.

16. The image sensor of claim 14 , wherein the continuous conductive layer is separated from a side surface of the first substrate by a third dielectric layer.

17. The image sensor of claim 14 , wherein the continuous conductive layer does not completely fill the second structure.

18. The image sensor of claim 14 , wherein:
the image sensor comprises a pixel region, a periphery region, a bonding pad region, and a scribe line region that are each different from one another;
the radiation-sensing region is disposed in the pixel region; and
the continuous conductive layer is disposed in the periphery region.

19. An image sensor, comprising:
a sensor portion that includes:
a first substrate having a first side and a second side opposite the first side;
a radiation-sensing region formed in the first substrate, the radiation-sensing region being configured to detect radiation that enters the first substrate through the second side;
a first interconnect structure disposed over the first side of the first substrate, the first interconnect structure including one or more first metal lines;
a first silicon nitride layer disposed over the first interconnect structure; and
a first silicon oxide

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen U-Ting
• Tsai Shu-Ting
• Ho Cheng-Ying
• Hsu Tzu-Hsuan
• Chou Shih Pei

Classifications

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title