Method of manufacturing thin-film transistor, thin-film transistor substrate, and flat panel display apparatus

Patent metadata

Field	Value
Publication number	US-10283529-B2
Application number	US-201615337401-A
Country	US
Kind code	B2
Filing date	Oct 28, 2016
Priority date	Dec 21, 2015
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A method of manufacturing a thin-film transistor includes forming an oxide semiconductor on a substrate, stacking an insulating layer and a metal layer on the substrate to cover the oxide semiconductor, forming a photosensitive pattern on the metal layer, forming a gate electrode by etching the metal layer using the photosensitive pattern as a mask, where a part of the gate electrode overlaps a first oxide semiconductor region of the oxide semiconductor, forming a gate insulating film by partially etching the insulating layer using the photosensitive pattern as a mask, where the gate insulating film includes a first insulating region with a first thickness under the photosensitive pattern and a second insulating region with a second thickness less than the first thickness, and performing plasma processing on the gate insulating film so that a second oxide semiconductor region of the oxide semiconductor under the second insulating region becomes conductive.

First claim

What is claimed is:

1. A method of manufacturing a thin-film transistor (TFT), the method comprising:
forming an oxide semiconductor pattern on a substrate;
sequentially stacking an insulating material layer and a metal layer on the substrate that covers the oxide semiconductor pattern;
forming a photosensitive pattern on the metal layer;
forming a gate electrode by wet etching the metal layer using the photosensitive pattern as a mask, wherein a side surface of the gate electrode is disposed inward from a side surface of the photosensitive pattern, and wherein at least one part of the gate electrode overlaps a first oxide semiconductor region of the oxide semiconductor pattern;
forming a gate insulating film by partially etching the insulating material layer using the photosensitive pattern as a mask, wherein the gate insulating film includes a first insulating region with a first thickness under the photosensitive pattern and a second insulating region with a second thickness less than the first thickness; and
performing plasma processing on the gate insulating film wherein a second oxide semiconductor region of the oxide semiconductor pattern under the second insulating region becomes conductive.

2. The method of claim 1 , wherein the plasma processing uses a hydrogen-containing gas.

3. The method of claim 1 , wherein the second thickness ranges from about 500 Å to about 1000 Å.

4. The method of claim 1 , further comprising:
removing the photosensitive pattern;
forming an interlayer insulating film on the gate electrode and the gate insulating film;
forming a contact hole through which a part of the second oxide semiconductor region is exposed, by etching the gate insulating film and the interlayer insulating film; and
forming an electrode through the contact hole that is electrically connected to the exposed part of the second oxide semiconductor region.

5. The method of claim 1 , wherein forming of gate insulating film comprises partially dry etching the insulating material layer using the photosensitive pattern as a mask, wherein an edge of the photosensitive pattern corresponds to a boundary between the first and second insulating regions.

6. The method of claim 1 , wherein the first insulating region comprises a central portion covered by the gate electrode and an edge portion not covered by the gate electrode.

7. The method of claim 6 , wherein performing the plasma processing comprises:
removing the photosensitive pattern; and
performing plasma processing using the gate electrode as a mask to form the oxide semiconductor pattern comprising the first oxide semiconductor region under the central portion of the first insulating region, a third oxide semiconductor region under the edge portion of the first insulating region, and the conductive second oxide semiconductor region under the second insulating region,
wherein the third semiconductor region has a resistance less than a resistance of the first oxide semiconductor region and greater than a resistance of the second oxide semiconductor region.

8. A thin-film transistor (TFT) substrate comprising:
a substrate;
an oxide semiconductor pattern disposed on the substrate and comprising a semiconducting first oxide semiconductor region and a conductive second oxide semiconductor region, wherein the oxide semiconductor pattern comprises a third oxide semiconductor region disposed between the first and second oxide semiconductor regions and that has a resistance less than a resistance of the first oxide semiconductor region and greater than a resistance of the second oxide semiconductor region;
a gate insulating film disposed on the substrate that covers the oxide semiconductor pattern and that comprises a first insulating region with a first thickness and a second insulating region with a second thickness less than the first thickness;
a gate electrode disposed on the first insulating region, wherein at least a part of the gate electrode overlaps the first oxide semiconductor region; and
an interlayer insulating film disposed on the gate insulating film that covers the gate electrode,
wherein the second oxide semiconductor region became conductive from a hydrogen gas based plasma process performed on the gate electrode and gate insulating film.

9. The TFT substrate of claim 8 , further comprising an electrode disposed in the interlayer insulating film and that is electrically connected to the second oxide semiconductor region through a contact plug that penetrates the interlayer insulating film and the gate insulating film.

10. The TFT substrate of claim 8 , wherein the second thickness ranges from about 500 Å to about 1000 Å.

11. The TFT substrate of claim 8 , wherein the first insulating region comprises a central portion covered by the gate electrode and an edge portion not covered by the gate electrode.

12. A flat panel display apparatus comprising:
a substrate;
an oxide semiconductor pattern disposed on the substrate and that comprises a semiconducting first oxide semiconductor region and a conductive second oxide semiconductor region, wherein the oxide semiconductor pattern comprises a third oxide semiconductor region disposed between the first and second oxide semiconductor regions and that has a resistance less than a resistance of the first oxide semiconductor region and greater than a resistance of the second oxide semiconductor region;
a gate insulating film disposed on the substrate that covers the oxide semiconductor pattern and that comprises a first insulating region with a first thickness and a second insulating region with a second thickness less than the first thickness;
a gate electrode disposed on the first insulating region, wherein at least a part of the gate electrode overlaps the first oxide semiconductor region;
an interlayer insulating film disposed on the gate insulating film that covers the gate electrode; and
an electrode disposed in the interlayer insulating film that is electrically connected to the second oxide semiconductor region through a contact plug that penetrates the interlayer insulating film and the gate insulating film.

13. The flat panel display apparatus of claim 12 , wherein the second oxide semiconductor region becomes conductive from a hydrogen gas based plasma process performed on the gate electrode and gate insulating film.

14. The flat panel display apparatus of claim 12 , wherein the second thickness ranges from about 500 Å to about 1000 Å.

15. The flat panel display apparatus of claim 12 , wherein the first insulating region comprises a central portion covered by the gate electrode and an edge portion not covered by the gate electrode.

16. The flat panel display apparatus of claim 12 , further comprising:
a pixel electrode electrically connected to the electrode;
a counter electrode that faces the pixel electrode; and
an organic emission layer disposed between the pixel electrode and the counter electrode.

17. The flat panel display apparatus of claim 12 , further comprising:
a pixel electrode electrically connected to the electrode;
a counter electrode that faces the pixel electrode; and
a liquid crystal layer disposed between the pixel electrode and the counter electrode.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Shinil
• Cho Hyunmin
• Kim Sanggab
• Yang Sunghoon
• Jeong Yugwang
• Ahn Byungdu

Classifications

• H01L27/1288

  Electricity · mapped topic

• H01L27/1225 Primary

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title