Substrate structure with selective surface finishes for flip chip assembly

Patent metadata

Field	Value
Publication number	US-10283480-B2
Application number	US-201615225389-A
Country	US
Kind code	B2
Filing date	Aug 1, 2016
Priority date	Aug 6, 2015
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate body;
a first metal structure formed on a top surface of the substrate body and having a first finish area and a second finish area, wherein the first finish area of the first metal structure is surrounded by the second finish area of the first metal structure;
a first surface finish provided over the first finish area of the first metal structure; and
a second surface finish that is different from the first surface finish and provided over the second finish area of the second metal structure.

2. The apparatus of claim 1 wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG).

3. The apparatus of claim 2 wherein the first surface finish comprises:
a first layer formed of gold with a thickness between 0.06 μm and 0.14 μm;
a second layer formed of palladium with a thickness between 0.08 μm and 0.16 μm; and
a third layer formed of nickel with a thickness between 0.3 μm and 0.5 μm, wherein the third layer is over the first finish area, the second layer is over the third layer, and the first layer is over the second layer.

4. The apparatus of claim 2 wherein the second surface finish is an organic surface protectorant (OSP).

5. The apparatus of claim 4 wherein a thickness of the second surface finish is between 0.2 μm and 0.4 μm.

6. The apparatus of claim 1 wherein the first surface finish is bussless NiAu or electroless palladium immersion gold (EPIG).

7. The apparatus of claim 1 wherein the first surface finish comprises gold and the second surface finish does not comprise gold.

8. The apparatus of claim 1 wherein the first surface finish is ENEPIG or EPIG, and the second surface finish is an OSP.

9. The apparatus of claim 1 further comprising a second metal structure formed on the top surface of the substrate body, wherein the first surface finish is provided over at least a portion of the second metal structure.

10. The apparatus of claim 9 wherein the first surface finish comprises gold and the second surface finish does not comprise gold.

11. The apparatus of claim 1 further comprising a second metal structure formed on the top surface of the substrate body, wherein the second surface finish is provided over at least a portion of the second metal structure.

12. The apparatus of claim 11 wherein the first surface finish comprises gold and the second surface finish does not comprise gold.

13. The apparatus of claim 1 wherein the first surface finish is a multilayer finish and the second surface finish is a single layer finish.

14. The apparatus of claim 1 wherein the first metal structure is formed of copper.

15. The apparatus of claim 1 wherein a thickness of the first metal structure is between 6 μm and 26 μm.

16. The apparatus of claim 1 further comprising:
a flip chip die having a die body and a first interconnect structure, wherein the first interconnect structure extends outward from the die body and is coupled to the first surface finish on the first metal structure.

17. The apparatus of claim 16 further comprising a second metal structure formed on the top surface of the substrate body, wherein:
at least a portion of the second metal structure is not covered by the first surface finish; and
the flip chip die further includes a second interconnect structure, wherein the second interconnect structure extends outward from the die body and is directly coupled to the second metal structure.

18. The apparatus of claim 1 further comprising a second metal structure that is formed on the top surface of the substrate body and has a first finish area and a second finish area, wherein:
the first surface finish is provided over the first finish area of the second metal structure; and
the second surface finish is provided over the second finish area of the second metal structure.

19. The apparatus of claim 18 wherein the first finish area of the second metal structure corresponds to a pad configured to receive a wirebond or interconnect structure of a die and the second finish area of the second metal structure corresponds to a conductive trace that connects the pad to another pad or via.

20. The apparatus of claim 19 wherein the first surface finish is ENEPIG or EPIG, and the second surface finish is an OSP.

Assignees

• Qorvo Us Inc

Inventors

• Morris Thomas Scott
• Hartmann Robert

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07234

  Using a reflow oven · CPC title

• H10W72/07221

  Aligning · CPC title