Method for assembling substrates by bonding indium phosphate surfaces

US10283364B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10283364-B2
Application numberUS-201615774122-A
CountryUS
Kind codeB2
Filing dateNov 7, 2016
Priority dateNov 9, 2015
Publication dateMay 7, 2019
Grant dateMay 7, 2019

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  1. Title

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  2. Abstract

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

The invention concerns an assembly method comprising the following steps: a) providing a first substrate comprising a first face made from crystalline indium phosphide, b) providing a second substrate comprising a second crystalline face different from the indium phosphide, c) forming an intermediate layer of crystalline indium phosphide on the second face of the second substrate, d) forming an assembly, via a direct bonding step, by bringing the first face of the first substrate into contact with the intermediate layer, the direct bonding step being carried out in an atmosphere having a pressure greater than 10−4 Pa, and preferably higher than 10−3 Pa, e) subjecting the assembly formed in step d) to heat treatment.

First claim

Opening claim text (preview).

The invention claimed is: 1. An assembly method, comprising: a) providing a first substrate comprising a first face made from crystalline indium phosphide, with the first face having a roughness less than 1 nm RMS, b) providing a second substrate comprising a second crystalline face different from the indium phosphide, c) forming an intermediate layer of crystalline indium phosphide on the second face of the second substrate, with the intermediate layer comprising an exposed surface having a roughness less than 1 nm RMS, c1) preparing the exposed surface of the intermediate layer, and the first face, in such a way as to render said exposed surface and said first face hydrophilic, said preparation being suitable for preserving the roughness of the exposed surface of the intermediate layer and of the first face, d) forming an assembly, via direct bonding at ambient temperature and without applying external mechanical pressure, by bringing the first face of the first substrate into contact with the intermediate layer, the direct bonding being carried out in an atmosphere having a pressure greater than 10 −4 Pa, and e) subjecting the assembly, formed in d), to a thermal treatment. 2. The method of claim 1 , wherein the first face and the second face of the second substrate are monocrystalline, and the intermediate layer is formed according to a coherent epitaxial growth. 3. The method of claim 2 , wherein e) is suitable for allowing a connection, at least partial, of the crystalline lattices to the interface formed by the first face and the intermediate layer. 4. The method of claim 1 , wherein d) is carried out according to one of the following conditions: in an atmosphere having a partial water pressure less than 10 −1 Pa, or in a partial vacuum, with the partial vacuum having a pressure less than 10 Pa. 5. The method of claim 1 , wherein c) is executed by a method of epitaxy. 6. The method of claim 1 , wherein e) is executed at a temperature between 200° C. and 600° C. 7. The method of claim 1 , wherein c1) is suitable for preserving the crystallinity of the intermediate layer and of the first face. 8. The method of claim 1 , wherein the second layer has a thickness less than 5 nm. 9. The method of claim 1 , wherein the first substrate is made from indium phosphide. 10. The method of claim 1 , wherein the second substrate comprises at least one material selected from the group consisting of gallium arsenide, silicon, silicon and germanium alloy, germanium, sapphire, alumina, silicon carbide, and an alloy of elements III and V.

Assignees

Inventors

Classifications

  • Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

  • with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

  • of die-attach connectors · CPC title

  • H10P10/128Primary

    by direct semiconductor to semiconductor bonding · CPC title

  • involving heating of the applied adhesive · CPC title

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What does patent US10283364B2 cover?
The invention concerns an assembly method comprising the following steps: a) providing a first substrate comprising a first face made from crystalline indium phosphide, b) providing a second substrate comprising a second crystalline face different from the indium phosphide, c) forming an intermediate layer of crystalline indium phosphide on the second face of the second substrate, d) forming an…
Who is the assignee on this patent?
Commissariat Energie Atomique, Soitec Silicon On Insulator
What technology area does this patent fall under?
Primary CPC classification H10P10/128. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 07 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).