Preemptive idle time read scans

Patent metadata

Field	Value
Publication number	US-10283205-B2
Application number	US-201715571232-A
Country	US
Kind code	B2
Filing date	Sep 30, 2017
Priority date	Sep 30, 2017
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

First claim

What is claimed is:

1. A memory device, comprising:
a NAND memory array; and
a memory controller operably coupled to the memory array, the memory controller to perform operations comprising:
scheduling a read scan operation on the memory array to occur upon a scheduled condition, wherein the read scan operation is to sample data at multiple locations of the memory array by performing reads at the multiple locations;
monitoring an operational state of the memory array, the operational state of the memory array including an active state corresponding to performing operations initiated from a host, and an idle state corresponding to an absence of operations initiated from the host; and
initiating the read scan operation in response to the operational state of the memory array entering the idle state, wherein the read scan operation is initiated to preemptively occur before the scheduled condition.

2. The memory device of claim 1 , wherein the read scan operation includes performing reads of sets of sampled pages or word lines of a plurality of blocks of the memory array, and wherein the reads are performed with different read voltages among the plurality of blocks.

3. The memory device of claim 2 , wherein the plurality of blocks are selected at random from within the NAND memory array.

4. The memory device of claim 1 , the operations further comprising:
scheduling a second read scan operation on the memory array to be conducted upon a second scheduled condition; and
initiating the second read scan operation in response to the operational state of the memory array not entering an idle state before the second scheduled condition, wherein the second read scan operation is initiated to occur upon the second scheduled condition.

5. The memory device of claim 1 , wherein the scheduled condition is a time determined from a scheduled time interval, and wherein the initiating of the read scan operation preemptively occurs upon entering the idle state during a predetermined time period prior to the scheduled condition.

6. The memory device of claim 1 , wherein the scheduled condition is a frequency-based condition, and wherein the scheduling of the read scan operation is performed in response to a frequency of error handling trigger events in a block exceeding a determined threshold.

7. The memory device of claim 1 , wherein the scheduled condition is a predetermined event, and wherein the scheduling of the read scan operation is performed in response to the predetermined event occurring within the memory controller, or in response to the predetermined event being identified from an attribute of: the memory array, the memory controller, or one or more modules in a firmware of the memory controller.

8. The memory device of claim 7 , wherein the predetermined event occurring within the memory controller corresponds to a block read count exceeding a determined block read count threshold.

9. The memory device of claim 1 , the operations further comprising:
initiating a wear leveling operation in response to the operational state of the memory array entering the idle state, wherein the wear leveling operation is initiated to occur after completion of the read scan operation.

10. The memory device of claim 1 , wherein in response to initiating the read scan operation to preemptively occur before the scheduled condition, the operations further comprise:
stopping the read scan operation in response to the operational state of the memory array entering the active state before the scheduled condition; and
resuming the read scan operation, in response to re-entering the idle state or in response to occurrence of the scheduled condition.

11. The memory device of claim 1 , wherein the operations initiated from the host include read operations or write operations, with the operations further comprising:
prioritizing the read scan operation over operations initiated from the host, in response to occurrence of the scheduled condition before a preemptive completion of the read scan operation.

12. The memory device of claim 1 , the operations further comprising:
initiating read voltage calibration of at least a portion of the memory array in response to data obtained from the reads conducted among the multiple locations of the memory array with the read scan operation.

13. The memory device of claim 12 , wherein the read scan operation performs sampling of a raw bit error rate (RBER) from the multiple locations in the memory array using multiple read voltages among the multiple locations, and wherein the read voltage calibration is performed in response to the RBER exceeding a predetermined threshold.

14. The memory device of claim 1 , wherein the memory array includes at least one of: single-level cell (SLC), multi-layer cell (MLC), triple-layer cell (TLC), or quad-layer cell (QLC) NAND memory cells.

15. The memory device of claim 1 , wherein the memory array is arranged into a stack of three-dimensional (3D) NAND dies.

16. A method for performing preemptive read scans in a memory device, the method comprising a plurality of operations performed by a memory controller upon a NAND memory array of the memory device, with the operations comprising:
scheduling a read scan operation on the memory array to be conducted upon a scheduled condition, wherein the read scan operation is to sample data at multiple locations of the memory array by performing reads at the multiple locations, and wherein the reads are performed with different read voltages among the multiple locations;
monitoring an operational state of the memory array, the operational state of the memory array including an active state corresponding to performing operations initiated from a host, and an idle state corresponding to an absence of operations initiated from the host; and
initiating the read scan operation in response to the operational state of the memory array entering the idle state, wherein the read scan operation is initiated to preemptively occur before the scheduled condition.

17. The method of claim 16 , wherein the read scan operation includes performing reads of sets of sampled pages or word lines of a plurality of blocks of the memory array, and wherein the plurality of blocks are selected at random from within the NAND memory array.

18. The method of claim 16 , wherein the scheduled condition is a time determined from a scheduled time interval, and wherein the initiating of the read scan operation preemptively occurs upon entering the idle state during a predetermined time period prior to the scheduled condition.

19. The method of claim 16 , wherein the scheduling of the read scan operation is performed in response to: a frequency of error handling trigger events in a block exceeding a determined threshold, an event occurring within the memory controller, or an event being identified from an attribute of: the memory array, the memory controller, or one or more modules in a firmware of the memory controller.

20. The method of claim 16 , wherein in response to initiating the read scan operation to preemptively occur before the scheduled condition, the operations further comprise:
stopping the read scan operation in response to the operational state of the memory array entering the active state before the scheduled condition; and
resuming the read scan operation, in response to re-entering the idle state or in response to occurrence of the scheduled condition.

21. The method of claim 16 , wherein the operations initiated from the host i

Assignees

• Micron Technology Inc

Inventors

• Malshe Ashutosh
• Singidi Harish
• Muchherla Kishore Kumar
• Miller Michael G
• Ratnam Sampath
• Zhang John
• Zhou Jie

Classifications

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C2207/2272

  Latency related aspects · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C2211/5644

  Multilevel memory comprising counting devices · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title