Store buffer supporting direct stores to a coherence point

Patent metadata

Field	Value
Publication number	US-10282298-B2
Application number	US-201715621759-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Jun 13, 2017
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A system that uses a write-invalidate protocol has two types of stores: a traditional store that operates using a write-back policy that snoops for copies of the cache line at lower cache levels, and a store that writes, using a coherent write-through policy, directly to the last-level cache without snooping the lower cache levels. A separate store buffer may be maintained in the processor for the coherent write-through operations. A special bit may be maintained in the entries of a store buffer that is used for both traditional write-back policy stores and for coherent write-through policy. This bit indicates that loads and stores older than the last speculative store in the store buffer are allowed to be performed.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of processor cores that share a common last-level cache, a first processor core being a one of the plurality of processor cores, the first processor core including a store buffer to hold, prior to a corresponding store transaction being issued by the first processor core, data blocks to be written to memory, the store buffer including, for each of the data blocks to be written to memory, a respective indicator that at least in part determines whether a respective data block is allowed to be modified prior to the first processor core issuing a store transaction to store the respective data block; and,
a memory order buffer to receive a first store transaction to store a first data block in the last-level cache, the memory order buffer to determine whether the first store transaction conflicts with a second store transaction.

2. The integrated circuit of claim 1 , wherein the memory order buffer is to send an indicator of whether the first store transaction conflicts with the second store transaction to the first processor core.

3. The integrated circuit of claim 2 , wherein the store buffer changes the respective indicator based at least in part on the indicator of whether the first store transaction conflicts with the second store transaction.

4. The integrated circuit of claim 3 , wherein, based at least in part on the indicator of whether the first store transaction conflicts with the second store transaction, the first processor core invalidates at least one store-to-load forward bypass of data associated with the first store transaction.

5. The integrated circuit of claim 4 , wherein, after the memory order buffer has resolved a conflict between the first store transaction and the second store transaction, the memory order buffer sends an indicator that the conflict has been resolved to the first processor core.

6. The integrated circuit of claim 5 , wherein, based at least in part on the indicator that the conflict has been resolved, the first processor core performs at least one store-to-load forward of at least some data associated with the first store transaction.

7. The integrated circuit of claim 2 , wherein, based at least in part on a resource limitation, the memory order buffer sends an indicator that the first store transaction conflicts with the second store transaction to the first processor core.

8. A method of operating a processing system, comprising:
receiving, at a store buffer, data blocks to be written to memory;
holding, by the store buffer and prior to a corresponding store transaction being issued by the store buffer, the data blocks to be written to memory, the store buffer including, for each of the data blocks to be written to memory, a respective indicator that at least in part determines whether a respective data block is allowed to be modified prior to the store buffer issuing a store transaction to store the respective data block;
issuing, by the store buffer and to a common last-level cache, at least a first store transaction to store a first data block; and,
determining, by the common last-level cache, whether the first store transaction conflicts with a second store transaction that has been received by the common last-level cache.

9. The method of claim 8 , further comprising:
based at least in part on the determination that the first store transaction conflicts with the second store transaction, sending, to the store buffer, an indicator that the first store transaction conflicts with at least the second store transaction.

10. The method of claim 9 , further comprising:
based at least in part on the indicator that the first store transaction conflicts with at least the second store transaction, changing the indicator that at least in part determines whether the first data block is allowed to be modified.

11. The method of claim 10 , further comprising:
based at least in part on the indicator that the first store transaction conflicts with at least the second store transaction, invalidating at least one store-to-load forward bypass of at least part of the first data block.

12. The method of claim 11 , further comprising:
based at least in part on the common last-level cache determining that the first store transaction no longer conflicts with a second store transaction, sending, to the store buffer, an indicator that the first store transaction no longer conflicts with another store transaction.

13. The method of claim 12 , further comprising:
based on the indicator that the first store transaction no longer conflicts with another store transaction, performing at least one store-to-load forward bypass of at least part of the first data block.

14. The method of claim 12 , further comprising:
based on the indicator that the first store transaction no longer conflicts with another store transaction, changing the indicator that at least in part determines whether the first data block is allowed to be modified.

15. The method of claim 12 , further comprising:
based at least in part on the determination that the first store transaction conflicts with the second store transaction, and determining that a threshold condition related to a resource for resolving conflicts between store transactions has been met, sending, to the store buffer, the indicator that the first store transaction conflicts with at least the second store transaction.

16. An integrated circuit, comprising:
a plurality of processor cores that share a common last-level cache, a first processor core being one of the plurality of processor cores, the first processor core including a first store buffer for direct to the last-level cache store transactions and a second store buffer for transactions that are to be processed by at least one lower level cache; and,
a memory order buffer to receive store transactions sent to the last-level cache by the first store buffer, the first store buffer to issue, to the memory order buffer, a first store transaction to store a first data block, the memory order buffer to determine the first store transaction conflicts with at least a second store transaction.

17. The integrated circuit of claim 16 , wherein the memory order buffer is to send an indicator that the first store transaction conflicts with at least the second store transaction to the first store buffer.

18. The integrated circuit of claim 17 , wherein, based at least in part on the indicator that the first store transaction conflicts with at least the second store transaction, the store buffer prevents at least one store-to-load forward bypass of at least part of the first data block.

19. The integrated circuit of claim 18 , wherein, based at least in part on a resource limitation, the memory order buffer is to send an indicator that the first store transaction conflicts with at least the second store transaction to the first store buffer.

20. The integrated circuit of claim 19 , wherein, based at least in part on the common last-level cache determining that the first store transaction no longer conflicts with another store transaction, sending, to the first store buffer, an indicator that the first store transaction no longer conflicts with another store transaction.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lai Patrick P

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/084

  with a shared cache · CPC title