Read technique for a bus interface system

Patent metadata

Field	Value
Publication number	US-10282269-B2
Application number	US-201514659328-A
Country	US
Kind code	B2
Filing date	Mar 16, 2015
Priority date	Dec 18, 2013
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

First claim

What is claimed is:

1. A bus interface system comprising:
a bus line;
a master bus controller coupled to the bus line, wherein the master bus controller is configured to:
store a read command;
generate a first set of data pulses along the bus line representing the read command;
generate a first error code based on the read command; and
generate a second set of data pulses along the bus line representing the first error code; and

a slave bus controller coupled to the bus line, wherein no other bus line connects the master bus controller and the slave bus controller, and wherein the slave bus controller is configured to:
decode the first set of data pulses representing the read command into a decoded read command;
generate a second error code based on the decoded read command;
decode the second set of data pulses representing the first error code into a decoded error code; and
perform a first error check on the decoded read command by comparing the decoded error code and the second error code.

2. The bus interface system of claim 1 wherein the master bus controller is further configured to:
transfer control of the bus line to the slave bus controller after transmitting the first set of data pulses and the second set of data pulses;
monitor the bus line to detect whether the slave bus controller is responsive during an error tolerance window; and
abort the read command when the slave bus controller is unresponsive during the error tolerance window.

3. The bus interface system of claim 1 wherein the master bus controller is configured to:
generate the first set of data pulses along the bus line representing the read command in accordance with a pulse width modulation (PWM) bus protocol; and
generate the second set of data pulses along the bus line representing the first error code in accordance with the PWM bus protocol.

4. The bus interface system of claim 3 wherein the slave bus controller is configured to:
decode the first set of data pulses in accordance with the PWM bus protocol; and
decode the second set of data pulses in accordance with the PWM bus protocol.

5. The bus interface system of claim 1 wherein:
the master bus controller is configured to generate the first error code based on the read command by being configured to implement a first cyclic redundancy code (CRC) algorithm on the read command so as to generate the first error code.

6. The bus interface system of claim 5 wherein the slave bus controller is configured to generate the second error code based on the decoded read command by being configured to implement a second CRC algorithm on the decoded read command so as to generate the second error code.

7. The bus interface system of claim 6 wherein the first CRC algorithm is the same as the second CRC algorithm.

8. The bus interface system of claim 6 wherein the slave bus controller is configured to perform the first error check on the decoded read command by being configured to compare the decoded error code and the second error code to detect whether the second error code and the decoded error code match.

9. The bus interface system of claim 8 wherein the slave bus controller comprises a first memory device configured to:
store slave data that includes data segments; and
assign first memory addresses to the data segments within the slave data.

10. The bus interface system of claim 9 wherein the read command identifies a first memory address of the first memory addresses and wherein the slave bus controller is further configured to generate a third set of data pulses along the bus line representing a data segment of the data segments at the first memory address when the decoded read command passes the first error check.

11. The bus interface system of claim 10 wherein the slave bus controller is further configured to abort the read command when the decoded read command fails the first error check.

12. The bus interface system of claim 10 wherein the slave bus controller is further configured to:
generate a third error code based on the data segment stored at the first memory address; and
transmit a fourth set of data pulses along the bus line representing the third error code.

13. The bus interface system of claim 12 wherein the master bus controller is further configured to:
decode the third set of data pulses into a decoded data segment;
decode the fourth set of data pulses into a second decoded error code;
generate a fourth error code based on the decoded data segment; and
perform a second error check on the decoded data segment by comparing the second decoded error code and the fourth error code.

14. The bus interface system of claim 13 wherein the master bus controller further comprises a second memory device configured to:
store a slave data image;
assign second memory addresses to the slave data image so that the second memory addresses each correspond to the first memory addresses; and
store the decoded data segment at a second memory address of the second memory addresses corresponding to the first memory address of the slave data when the decoded data segment passes the second error check.

15. The bus interface system of claim 1 , wherein the bus interface system is a one wire bus interface system.

16. A method of operating a bus interface system that includes a master bus controller and a slave bus controller coupled to a single bus line, wherein no other bus line connects the master bus controller and the slave bus controller, the method comprising:
generating a first set of data pulses along the single bus line representing a read command with the master bus controller;
generating a first error code based on the read command;
generating a second set of data pulses along the single bus line representing the first error code with the master bus controller;
decoding the first set of data pulses representing the read command into a decoded read command with the slave bus controller;
generating a second error code based on the decoded read command with the slave bus controller;
decoding the second set of data pulses representing the first error code into a decoded error code with the slave bus controller; and
performing a first error check on the decoded read command by comparing the decoded error code and the second error code.

17. The method of claim 16 wherein:
generating the first set of data pulses along the bus line is in accordance with a pulse width modulation (PWM) bus protocol; and
generating the second set of data pulses along the bus line is in accordance with the PWM bus protocol.

18. The method of claim 17 wherein:
decoding the first set of data pulses is in accordance with the PWM bus protocol; and
decoding the second set of data pulses is in accordance with the PWM bus protocol.

19. The method of claim 16 , wherein the bus interface system is a one wire bus interface system.

20. A bus interface system comprising:
a bus line;
a slave bus controller coupled to the bus line, wherein the slave bus controller comprises a first memory device configured to store slave data having data segments assigned to first memory addresses, the slave bus controller is configured to:
generate a first set of data pulses along the bus line representing a data segment within the slave data at a first memory address of the first memory addresses;
generate a first error code based on the data segment; and
generate a second set of data pulses along the bus line representing the first error code; and

a master bus

Assignees

• Rf Micro Devices Inc
• Qorvo Us Inc

Inventors

• Ngo Christopher Truong
• Hietala Alexander Wayne

Classifications

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• H04L1/0041

  Arrangements at the transmitter end · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• G06F13/3625

  using a time dependent access · CPC title