Digital controlled delay line

Patent metadata

Field	Value
Publication number	US-10277215-B2
Application number	US-201715581033-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Apr 28, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Digital controlled delay lines are provided. A digital controlled delay line includes a plurality of delay cells coupled in a chain forming a propagation path to propagate an input signal and to delay the input signal by a delay time. The propagation path is formed when a single delay cell is operated in a feedback mode, the delay cells previous to the single delay cell in the chain are operated in a propagation mode, a subsequent delay cell following the single delay cell in the chain is operated in a standby mode, and the delay cells following the first subsequent delay cell in the chain are operated in an idle mode.

First claim

What is claimed is:

1. A digital controlled delay line, comprising:
a plurality of delay cells coupled in a chain, forming a first propagation path to propagate an input signal and to delay the input signal by a first delay time,
wherein each of the delay cells is configured to operate in:
a propagation mode for propagating a first signal from a previous stage of a delay cell to a subsequent stage of the delay cell and propagating a second signal from the subsequent stage of the delay cell to the previous stage of the delay cell;
a feedback mode for propagating the first signal from the previous stage of the delay cell to the subsequent stage of the delay cell and back to the previous stage of the delay cell;
a standby mode for propagating the first signal from the previous stage of the delay cell to the subsequent stage of the delay cell, and providing a first high-impedance output to the previous stage of the delay cell; or
an idle mode for providing the first high-impedance output to the previous stage of the delay cell, and providing a second high-impedance output to the subsequent stage of the delay cell,
wherein the first propagation path is formed when a single delay cell in the chain is operated in the feedback mode, the delay cells previous to the single delay cell in the chain are operated in the propagation mode, a first subsequent delay cell following the single delay cell in the chain is operated in the standby mode, and the delay cells following the first subsequent delay cell in the chain are operated in the idle mode.

2. The digital controlled delay line as claimed in claim 1 , wherein each of the delay cells comprises:
a first tri-state inverter controlled by a first control signal, having an input terminal coupled to the previous stage of the delay cell, and an output terminal coupled to the subsequent stage of the delay cell;
a second tri-state inverter controlled by a second control signal, having an input terminal coupled to the subsequent stage of the delay cell, and an output terminal coupled to the previous stage of the delay cell; and
a third tri-state inverter controlled by a third control signal, having an input terminal coupled to the output terminal of the first tri-state inverter, and an output terminal coupled to the input terminal of the second tri-state inverter.

3. The digital controlled delay line as claimed in claim 2 , wherein the first delay time is proportional to the number of enabled first, second, and third tri-state inverters of the delay cells on the first propagation path,
wherein in the propagation mode, the first and second tri-state inverters are enabled by the first and second control signals, respectively, and the third tri-state inverter is disabled by the third control signal,
wherein in the feedback mode, the first, second and third tri-state inverters are enabled by the first, second and third control signals, respectively,
wherein in the standby mode, the first and third tri-state inverters are enabled by the first and third control signals, respectively, and the second tri-state inverter is disabled by the second control signal,
wherein in the idle mode, the first, second and third tri-state inverters are disabled by the first, second and third control signals, respectively.

4. The digital controlled delay line as claimed in claim 1 , wherein the delay cells in the chain form a second propagation path to propagate the input signal and to delay the input signal by a second delay time, wherein the second propagation path is formed when a pair of delay cells are operated in the feedback mode, and the delay cells previous to the pair of delay cells in the chain are operated in the propagation mode, wherein the pair of delay cells comprises the single delay cell and the first subsequent delay cell.

5. The digital controlled delay line as claimed in claim 4 , wherein when the second propagation path is formed, a second subsequent delay cell following the first subsequent delay cell in the chain is operated in the standby mode, and the delay cells following the second subsequent delay cell in the chain are operated in the idle mode.

6. The digital controlled delay line as claimed in claim 4 , wherein the first delay time is shorter than the second delay time.

7. The digital controlled delay line as claimed in claim 4 , wherein the number of enabled first, second, and third tri-state inverters of the delay cells on the first propagation path is N, and the first delay time is proportional to N and the second delay time is proportional to N+1.

8. A digital controlled delay line, comprising:
a first inverter, having an input terminal for receiving an input signal;
a second inverter, having an input terminal coupled to the input terminal of the first inverter;
a third inverter, having an input terminal coupled to an output terminal of the second inverter;
a fourth inverter, having an input terminal coupled to an output terminal of the third inverter; and
a fifth inverter, having an input terminal coupled to an output terminal of the first inverter for receiving the input signal through the first inverter and an output terminal of the fourth inverter for receiving the input signal through the second, third and fourth inverters, and an output terminal for providing an output signal.

9. The digital controlled delay line as claimed in claim 8 , further comprising:
a sixth inverter, having an input terminal coupled to an output terminal of the second inverter;
a seventh inverter, having an input terminal coupled to an output terminal of the sixth inverter; and
an eighth inverter, having an input terminal coupled to an output terminal of the seventh inverter, and an output terminal coupled to the input terminal of the fourth inverter.

10. The digital controlled delay line as claimed in claim 9 , wherein the inverters are tri-state inverters controlled by corresponding control signals, and when the first to seventh inverters are enabled and the eighth inverter is disabled by corresponding control signals, the input signal is propagated and delayed by a first delay time to provide the output signal.

11. The digital controlled delay line as claimed in claim 10 , wherein when the second to seventh inverters are enabled and the first and the eighth inverter are disabled by corresponding control signals, the input signal is propagated and delayed by a second delay time to provide the output signal, and the second delay time is longer than the first delay time.

12. The digital controlled delay line as claimed in claim 8 , further comprising:
at least one ninth inverter, having an output terminal for providing the input signal; and
at least one tenth inverter, having an input terminal for receiving the output signal.

13. A digital controlled delay line, comprising:
a plurality of first tri-state inverters coupled in series and controlled by a first set of control signals;
a plurality of second tri-state inverters coupled in series and controlled by a second set of control signals; and
a plurality of third tri-state inverters controlled by a third set of control signals, wherein a third tri-state inverter of the third tri-state inverters has an input terminal coupled to an input terminal of an individual first tri-state inverter, and an output terminal coupled to an output terminal of an individual second tri-state inverter,
wherein when one of the third tri-state inverters is enabled, an input signal is propagated and delayed by a first delay time via a first propagation path, and the first propagation path is formed by the enabled third tri-state inverter, each of the first tri-state inverters havin

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Meng-Ting
• Tsai Chien-Chun
• Lin Mu-Shan
• Huang Wen-Hung
• Chen Yu-Chi

Classifications

• H03K5/131 Primary

  Digitally controlled · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title