Programmable delay circuit for low power applications

Patent metadata

Field	Value
Publication number	US-9490785-B1
Application number	US-201514705733-A
Country	US
Kind code	B1
Filing date	May 6, 2015
Priority date	May 6, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass or block a signal on the forward path depending on a logic state of a respective select signal. Each of the delay stages also comprises a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or route the signal on the forward path to the return path depending on the logic state of the respective select signal. Output logic states of the delay gates and the multiplexers may remain static during a change in the delay setting of the delay circuit to reduce glitch.

First claim

What is claimed is:

1. A delay circuit, comprising:
a plurality of delay stages coupled in series, wherein each of the delay stages comprises:
a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass a signal on the forward path or to block the signal on the forward path depending on a logic state of a respective select signal; and
a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or to route the signal on the forward path to the return path depending on the logic state of the respective select signal;

wherein the delay gates and the multiplexers in all of the plurality of delay stages are configured to maintain static output logic states regardless of changes to logic states of one or more of the select signals during a change in a delay setting of the delay circuit.

2. The delay circuit of claim 1 , wherein the delay gates are inverting and the multiplexers are inverting.

3. The delay circuit of claim 2 , wherein one of the multiplexers comprises:
a first tri-state inverter having a first input coupled to an output of another one of the multiplexers on the return path, a second input configured to receive the respective select signal, and a first output; and
a second tri-state invert having a third input coupled to an output of one of the delay gates on the forward path, a fourth input configured to receive an inverse of the respective select signal, and a second output coupled to the first output of the first tri-state inverter.

4. A delay circuit, comprising:
a plurality of delay stages coupled in series, wherein each of the delay stages comprises:
a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass a signal on the forward path or to block the signal on the forward path depending on a logic state of a respective select signal; and
a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or to route the signal on the forward path to the return path depending on the logic state of the respective select signal;

wherein the delay gates of the delay stages comprise alternating NAND gates and NOR gates on the forward path.

5. The delay circuit of claim 4 , wherein one of the NAND gates comprises:
a first tri-state inverter having a first input coupled to an output of a first one of the NOR gates on the forward path, a second input configured to receive the respective select signal, and an output coupled to an input of a second one of the NOR gates on the forward path; and
a pull-up transistor having a source coupled to a supply rail, a gate configured to receive the respective select signal, and a drain coupled to the output of the first tri-state inverter.

6. The delay circuit of claim 5 , wherein the one of the NAND gates further comprises a dummy transistor having a drain coupled to the output of the first tri-state inverter, and a gate and a source that are tied together to a ground.

7. The delay circuit of claim 5 , wherein the second one of the NOR gates comprises:
a second tri-state inverter having a first input coupled to the output of the one of NAND gate on the forward path, a second input configured to receive the respective select signal, and an output coupled to an input of another one of the NAND gates on the forward path; and
a pull-down transistor having a drain coupled to the output of the second tri-state inverter, a gate configured to receive an inverse of the respective select signal, and a source coupled to a ground.

8. The delay circuit of claim 5 , wherein the first tri-state inverter comprises:
an inverter coupled to the output of the first one of the NOR gates on the forward path, and an output; and
a transmission gate coupled between the output of the inverter and the input of the second one of the NOR gates on the forward path, wherein the transmission gate is configured to pass or block a signal at the output of the inverter depending on the logic state of the respective select signal.

9. The delay circuit of claim 4 , wherein one of the NOR gates comprises:
a tri-state inverter having first input coupled to the output of a first one of the NANDs gate on the forward path, a second input configured to receive the respective select signal, and an output coupled to an input of second one of the NAND gates on the forward path; and
a pull-down transistor having a drain coupled to the output of the tri-state inverter, a gate configured to receive an inverse of the respective select signal, and a source coupled to a ground.

10. The delay circuit of claim 9 , wherein the one of the NOR gates further comprises a dummy transistor having a drain coupled to the output of the tri-state inverter, and a gate and a source that are tied together to a supply rail.

11. A delay system, comprising:
a delay circuit comprising a plurality of delay stages coupled in series, wherein each of the delay stages comprises:
a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass a signal on the forward path or to block the signal on the forward path depending on a logic state of a respective select signal; and
a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or to route the signal on the forward path to the return path depending on the logic state of the respective select signal; and

a controller configured to change logic states of one or more of the select signals to change a delay setting of the delay circuit, wherein the delay gates and the multiplexers in all of the plurality of delay stages are configured to maintain static output logic states regardless of changes by the controller to the logic states of the one or more of the select signals.

12. The delay system of claim 11 , wherein the delay gates are inverting and the multiplexers are inverting.

13. The delay system of claim 12 , wherein one of the multiplexers comprises:
a first tri-state inverter having a first input coupled to an output of another one of the multiplexers on the return path, a second input configured to receive the respective select signal, and a first output; and
a second tri-state invert having a third input coupled to an output of one of the delay gates on the forward path, a fourth input configured to receive an inverse of the respective select signal, and a second output coupled to the first output of the first tri-state inverter.

14. The delay system of claim 11 , further comprising a gating circuit configured to selectively gate an input of the delay circuit under the control of the controller, wherein the controller is configured to command the gating circuit to gate the input of the delay circuit, to wait for a data signal or a clock signal in the delay circuit to flush out of the delay circuit while the input of the delay circuit is gated, and, after the signal is flushed out, to change the logic states of the one or more of the select signals to change the delay setting of the delay circuit.

15. The delay system of claim 11 , further comprising a gating circuit configured to selectively gate an output of the delay circuit under the control of the controller, wherein the controller is configured to command the gating circuit to gate the output of the delay circuit, to set the delay setting of the delay circuit to a first delay, and, after the delay setting of the delay circuit is set to the first delay, to change the logic states of the one or more of the se

Assignees

• Qualcomm Inc
• Qualcomm Inc

Inventors

• Sridhar Shraddha
• Diffenderfer Jan Christian
• Singh Guneet
• Fertsch Michael Thomas

Classifications

• H03K5/131

  Digitally controlled · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03K5/06 Primary

  by the use of delay lines or other analogue delay elements · CPC title

• H03K3/0315

  Ring oscillators · CPC title