Wrap-around contacts formed with multiple silicide layers

Patent metadata

Field	Value
Publication number	US-10276442-B1
Application number	US-201815993017-A
Country	US
Kind code	B1
Filing date	May 30, 2018
Priority date	May 30, 2018
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A first field-effect transistor has a first source/drain region, and a second field-effect transistor has a second source/drain region. A first silicide layer is arranged to wrap around the first source/drain region, and a second silicide layer is arranged to wrap around the second source/drain region. The first silicide layer contains a first metal, and the second silicide layer contains a second metal different from the first metal.

First claim

What is claimed is:

1. A method comprising:
epitaxially growing a first source/drain region of a first field-effect transistor;
epitaxially growing a second source/drain region of a second field-effect transistor;
epitaxially growing a first epitaxial semiconductor layer arranged to wrap around the first source/drain region;
epitaxially growing a second epitaxial semiconductor layer arranged to wrap around the second source/drain region;
forming an interlayer dielectric layer over the first source/drain region and the second source/drain region;
forming a first opening extending through the interlayer dielectric layer to the first epitaxial semiconductor layer and a second opening extending through the interlayer dielectric layer to the second epitaxial semiconductor layer;
removing the first epitaxial semiconductor layer selective to the second epitaxial semiconductor layer and the first source/drain region with a first selective etching process;
after removing the first epitaxial semiconductor layer, forming a first silicide layer arranged to wrap around the first source/drain region;
removing the second epitaxial semiconductor layer selective to the second source/drain region with a second selective etching process; and
after removing the second epitaxial semiconductor layer, forming a second silicide layer arranged to wrap around the second source/drain region,
wherein the first opening provides access to the first epitaxial semiconductor layer, the second opening provides access to the second epitaxial semiconductor layer, the first epitaxial semiconductor layer has a first composition, the second epitaxial semiconductor layer has a second composition different from the first composition, the first silicide layer comprises a first metal, and the second silicide layer comprises a second metal different from the first metal.

2. The method of claim 1 wherein the first source/drain region is epitaxially grown by a first epitaxial growth process, and the second source/drain region is epitaxially grown by a second epitaxial growth process after the first source/drain region is epitaxially grown.

3. The method of claim 1 wherein the first epitaxial semiconductor layer is epitaxially grown on the first source/drain region before the second epitaxial semiconductor layer is epitaxially grown on the second source/drain region.

4. The method of claim 1 wherein the second epitaxial semiconductor layer is removed after removing the first epitaxial semiconductor layer and after forming the first silicide layer.

5. The method of claim 1 wherein the first silicide layer is formed in the first opening and the second opening in the interlayer dielectric layer.

6. The method of claim 5 further comprising:
before removing the second epitaxial semiconductor layer, removing the first silicide layer from the second opening in the interlayer dielectric layer.

7. The method of claim 1 wherein the first silicide layer is formed with a deposition process in a confined space surrounding one or more sidewalls and a top surface of the first source/drain region, and the confined space is formed by removing the first epitaxial semiconductor layer.

8. The method of claim 7 wherein the first silicide layer is conformally formed with the deposition process in a first portion of the confined space, and the method further comprises:
depositing a metal fill layer having a first portion in the first opening and a second portion in a second portion of the confined space,
wherein the first silicide layer is arranged between the metal fill layer and the first source/drain region.

9. The method of claim 1 wherein the second silicide layer is formed with a deposition process in a confined space surrounding one or more sidewalls and a top surface of the first source/drain region, and the confined space is formed by removing the second epitaxial semiconductor layer.

10. The method of claim 9 wherein the second silicide layer is conformally formed with the deposition process in a first portion of the confined space, and the method further comprises:
depositing a metallization layer having a first portion in the second opening in the interlayer dielectric layer and a second portion in a second portion of the confined space,
wherein the second silicide layer is arranged between the second portion of the metallization layer and the second source/drain region.

11. The method of claim 1 wherein the first source/drain region has one or more side surfaces and a top surface, and the first silicide layer is formed in direct contact with the one or more side surfaces and the top surface of the first source/drain region.

12. The method of claim 11 further comprising:
forming a conformal dielectric layer on the first epitaxial semiconductor layer,
wherein the conformal dielectric layer is arranged to wrap about the one or more side surfaces and the top surface of the first epitaxial semiconductor layer, the first epitaxial semiconductor layer is removed by the first selective etching process selective to the conformal dielectric layer to form a confined space between the conformal dielectric layer and the first source/drain region, and the first silicide layer is formed in the confined space after removing the first epitaxial semiconductor layer.

13. The method of claim 1 further comprising:
exposing the first epitaxial semiconductor layer and the second epitaxial semiconductor layer to the first selective etching process respectively through the first opening and the second opening in the interlayer dielectric layer.

14. The method of claim 13 further comprising:
after forming the first silicide layer, depositing a metal fill layer in the first opening and the second opening in the interlayer dielectric layer;
recessing the metal fill layer inside the first opening and the second opening in the interlayer dielectric layer; and
before removing the second epitaxial semiconductor layer, removing the metal fill layer from the second opening in the interlayer dielectric layer.

15. The method of claim 1 wherein the first source/drain region comprises silicon-germanium doped to have p-type conductivity type, the second source/drain region comprises silicon doped to have n-type conductivity type, the first metal comprises nickel or a combination of nickel and platinum, and the second metal comprises titanium.

16. The method of claim 1 further comprising:
forming a first plurality of nanosheet channel layers arranged in a first layer stack; and
forming a second plurality of nanosheet channel layers arranged in a second layer stack,
wherein the first source/drain region is epitaxially grown from the first plurality of nanosheet channel layers, and the second source/drain region is epitaxially grown from the second plurality of nanosheet channel layers.

17. A structure comprising:
a first field-effect transistor including a first source/drain region with a top surface and one or more side surfaces;
a second field-effect transistor including a second source/drain region with a top surface and one or more side surfaces;
a first contact including a lower portion coupled with the first source/drain region and an upper portion coupled by the lower portion with the first source/drain region, the lower portion of the first contact including a first silicide layer arranged to wrap around the top surface and the one or more side surfaces of the first source/drain region, and the upper portion of the first contact including a first portion of a metallization layer; and
a second contact including a low

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Frougier Julien
• Cheng Kangguo
• Carr Adra
• Loubet Nicolas

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L27/088

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L21/823412

  Electricity · mapped topic