MRAM device and fabrication method

Patent metadata

Field	Value
Publication number	US-9564577-B1
Application number	US-201514942502-A
Country	US
Kind code	B1
Filing date	Nov 16, 2015
Priority date	Nov 16, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A magnetoresistive random access memory (MRAM) device comprises a bottom electrode over a tapered bottom via, a tapered magnetic tunnel junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and a top via over the top electrode. The top via, top electrode, MTJ, bottom electrode, and bottom via (and electrical interfaces therebetween) are substantially aligned along a common vertical axis. The bottom via has a taper angle of about 120° to about 150°. The MTJ has a taper angle of about 70° to about 85°. The MTJ is isolated and protected with dual sidewall spacers.

First claim

What is claimed is:

1. A magnetoresistive random access memory (MRAM) device, comprising:
a bottom electrode over a conductive via, the conductive via having a first tapered sidewall;
a magnetic tunnel junction (MTJ) over the bottom electrode, the MTJ having a second tapered sidewall;
a top electrode over the MTJ;
a first dielectric material adjacent to the top electrode and the MTJ; and
a second dielectric material adjacent to at least a portion of the first dielectric material, wherein the first dielectric material and the second dielectric material comprise different material layers, and at least a portion of a first sidewall of the first dielectric material distally disposed from the top electrode is substantially adjoined with a second sidewall of the second dielectric material distally disposed from the top electrode.

2. The device of claim 1 , wherein the first tapered sidewall comprises a taper angle of about 120° to about 150°.

3. The device of claim 1 , wherein the second tapered sidewall comprises a taper angle of about 70° to about 85°.

4. The device of claim 1 , wherein at least one of:
the first dielectric material comprises a first spacer having a first width between about 15 nm to about 50 nm; or
the second dielectric material comprises a second spacer having a second width between about 5 nm to about 20 nm.

5. The device of claim 1 , wherein:
the first dielectric material comprises at least one of SiC, SiN, SiOC, or SiO 2 ; and
the second dielectric material comprises at least one of SiC, SiN, SiOC, or SiO 2 .

6. The device of claim 1 , wherein at least one of the conductive via, the bottom electrode, or the top electrode comprises at least one of W, TiN, TaN, Ti, Ta, Cu, or Al.

7. A method of fabricating a magnetoresistive random access memory (MRAM) device, the method comprising:
depositing a first dielectric layer over a substrate;
removing a portion of the first dielectric layer to form an opening;
filling the opening with a conductive material to form a conductive via;
depositing a conductive layer over the conductive via;
removing a laterally disposed portion of the conductive layer to form a bottom electrode;
forming a magnetic tunnel junction (MTJ) over the bottom electrode;
forming a top electrode over the MTJ;
conformally depositing a second dielectric layer over the top electrode, the MTJ, and the bottom electrode;
conformally depositing a third dielectric layer over the second dielectric layer;
removing at least a portion of the second dielectric layer to form a first spacer; and
removing at least a portion of the third dielectric layer to form a second spacer, wherein at least a portion of the first spacer is disposed above an upper-most surface of the second spacer.

8. The method of claim 7 , wherein the opening comprises a tapered sidewall having an interiorly disposed taper angle greater than 90°.

9. The method of claim 7 , wherein removing the laterally disposed portion of the conductive layer forms a tapered sidewall of the bottom electrode.

10. The method of claim 7 , wherein forming the MTJ comprises removing a laterally disposed portion of the MTJ to form a tapered sidewall of the MTJ.

11. The method of claim 7 , wherein:
the first spacer has a width of about 15 nm to about 50 nm; and
the second spacer has a width of about 5 nm to about 20 nm.

12. The method of claim 8 , wherein the tapered sidewall comprises an interiorly disposed taper angle of about 120° to about 150°.

13. The method of claim 10 , wherein the tapered sidewall of the MTJ comprises an interiorly disposed taper angle less than 90°.

14. The method of claim 13 , wherein the tapered sidewall of the MTJ comprises an interiorly disposed taper angle of about 70° to about 85°.

15. A magnetoresistive random access memory (MRAM) device, comprising:
a bottom via over a substrate;
a bottom electrode over the bottom via;
a magnetic tunnel junction (MTJ) over the bottom electrode;
a top electrode over the MTJ;
a top via over the top electrode;
a first spacer comprising a first dielectric material annularly disposed around the top electrode and the MTJ, wherein the first spacer comprises a bottom surface, the first spacer overlies the bottom electrode, a first lateral extent of the bottom surface is substantially equal to a second lateral extent of the bottom electrode, and the bottom surface is in physical contact with the bottom electrode; and
a second spacer comprising a second dielectric material annularly disposed around a portion of the first dielectric material.

16. The device of claim 15 , wherein a sidewall profile of the bottom via has an interiorly disposed taper angle of about 120° to about 150°.

17. The device of claim 15 , wherein a sidewall profile of the MTJ has an interiorly disposed taper angle of about 70° to about 85°.

18. The device of claim 15 , wherein the first dielectric material comprises a first spacer having a width of about 15 nm to about 50 nm.

19. The device of claim 15 , wherein the second dielectric material comprises a second spacer having a width of about 5 nm to about 20 nm.

20. The device of claim 15 , wherein the top electrode, MTJ, bottom electrode, and via are substantially aligned along a common vertical axis.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Chern-Yow
• Liu Shih-Chang

Classifications

• H01L43/02 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H10N50/10 Primary

  Magnetoresistive devices · CPC title