Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-10269748-B2
Application number	US-201615061992-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	May 29, 2015
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A semiconductor device includes a semiconductor substrate provided with a through hole that extends therethrough from a first surface to a second surface on a side opposite to the first surface, a device layer provided at the first surface of the semiconductor substrate which includes an electrode, an insulating layer that covers the device layer, a first through electrode that extends through the insulating layer, an insulating layer that extends from the second surface of the semiconductor substrate to a bottom surface of the through hole through an inner surface of the through hole of the semiconductor substrate, and in which the portion thereof in contact with the bottom surface has a tapered shape, and a second through electrode electrically connected to the electrode in the device layer that is exposed to the bottom surface of the through hole.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface opposite the first surface;
a device layer on the first surface of the semiconductor substrate;
a wiring in the device layer between a first side surface of the device layer and a second side surface of the device layer, the first side surface of the device layer contacting the first surface of the semiconductor substrate, the second side surface of the device layer being opposite the first side surface;
a first insulating layer on the second side surface of the device layer;
a first through electrode extending through the first insulating layer and contacting the device layer on the second side surface;
a second through electrode extending through a hole in the semiconductor substrate from the first surface to the second surface, the second through electrode contacting the wiring in the device layer at the bottom of the hole; and
a second insulating layer extending from the second surface of the semiconductor substrate to the bottom of the hole along an inner wall of the hole, the second insulating layer being between the semiconductor substrate and the second through electrode, wherein a portion of the second insulating layer at the bottom of the hole and contacting the first side surface of the device layer has a tapered surface with an inclination angle with respect to the first side surface of the device layer that is greater than 0°.

2. The semiconductor device according to claim 1 , wherein the inclination angle is less than 75°.

3. The semiconductor device according to claim 1 , wherein the inclination angle is between 30° and 60°.

4. The semiconductor device according to claim 1 , wherein the second through electrode comprises:
a first metal layer extending into contact with the wiring in the device layer through an opening in the second insulating layer at the bottom of the hole;
a second metal layer formed on the first metal layer; and
a third metal layer formed on the second metal layer.

5. The semiconductor device according to claim 1 , wherein the second insulating layer includes:
a first silicon nitride film formed on the second surface of the semiconductor substrate; and
a second silicon nitride film extending from the first silicon nitride film to the bottom of the hole through the interior of the hole, wherein the portion of the second silicon nitride film at the bottom of the hole is tapered.

6. The semiconductor device according to claim 1 , further comprising a bonding material on an end of the second through electrode opposite the bottom of the hole.

7. The semiconductor device according to claim 1 , wherein the semiconductor substrate has a thickness of 50 micrometers or less.

Assignees

• Toshiba Memory Corp

Inventors

• Kume Ippei
• Uchida Kengo

Classifications

• H10W72/9226

  with via interconnections · CPC title

• H10W72/01955

  by using masks · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title