Increased contact alignment tolerance for direct bonding

Patent metadata

Field	Value
Publication number	US-10269708-B2
Application number	US-201715853085-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Dec 18, 2015
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.

First claim

What is claimed is:

1. A bonded structure comprising:
a first semiconductor element comprising a conductive first contact structure and a non-metallic first bonding region proximate the first contact structure, the first contact structure comprising a conductive first grid pattern of multiple intersecting lines; and
a second semiconductor element comprising a conductive second contact structure and a non-metallic second bonding region proximate the second contact structure, the second contact structure comprising a conductive second grid pattern of multiple intersecting lines,
wherein the first bonding region is in contact with and directly bonded to the second bonding region, and
wherein the first grid pattern intersects and directly contacts the second grid pattern.

2. The bonded structure of claim 1 , wherein the first grid pattern is directly bonded to the second grid pattern at one or more intersections between the first grid pattern and the second grid pattern.

3. The bonded structure of claim 1 , wherein at least one of the first and second conductive contact structures comprises at least one of a metal and a conductively-doped semiconductor material.

4. The bonded structure of claim 1 , wherein at least one of the first and second bonding regions comprises at least one of a semiconductor material and an insulating material.

5. The bonded structure of claim 4 , wherein at least one of the first and second bonding regions comprises silicon oxide.

6. The bonded structure of claim 1 , wherein the first bonding region is directly bonded to the second bonding region along an interface, the interface between the first bonding region and the second bonding region extending substantially to the first and second conductive contact structures.

7. The bonded structure of claim 1 , wherein a pitch of lines of the first grid pattern is in a range of 1 micron to 10 microns.

8. A bonded structure comprising:
a first semiconductor element comprising a conductive first contact structure and a non-metallic first bonding region surrounding the first contact structure, the first contact structure comprising a conductive first elongate contact feature, the first elongate contact feature comprising a semiconductor material heavily doped with an electrical dopant, the first bonding region comprising a lightly doped or an undoped semiconductor material; and
a second semiconductor element comprising a conductive second contact structure and a non-metallic second bonding region surrounding the second contact structure, the second contact structure comprising a conductive second contact feature,
wherein the first bonding region is in contact with and directly bonded to the second bonding region, and
wherein the first elongate contact feature directly contacts and is directly bonded to the second contact feature.

9. The bonded structure of claim 8 , wherein the first elongate contact feature is oriented non-parallel with the second contact feature, the second contact feature comprising an elongate contact feature.

10. The bonded structure of claim 8 , wherein the non-metallic second bonding region comprises a lightly doped or an undoped semiconductor material.

11. The bonded structure of claim 8 , wherein the conductive second contact feature comprises a semiconductor material heavily doped with an electrical dopant.

12. The bonded structure of claim 8 , wherein the first contact structure comprises a plurality of lines in a grid pattern.

13. The bonded structure of claim 12 , wherein the second contact structure comprises a plurality of lines in a grid pattern.

14. The bonded structure of claim 8 , wherein the first contact structure defines a boundary disposed about a central region and a plurality of conductive segments extending outwardly from the central region.

15. The bonded structure of claim 14 , further comprising a plurality of lateral connectors that connect the plurality of conductive segments.

16. The bonded structure of claim 8 , wherein the first elongate contact feature has a length and a width, the length being at least twice the width.

17. The bonded structure of claim 8 , wherein a length of the first elongate contact feature is in a range of 5 microns to 50 microns.

18. The bonded structure of claim 17 , further comprising a through-silicon via (TSV) disposed within the first semiconductor element below an intersection of the first elongate contact feature and the second contact feature.

19. The bonded structure of claim 18 , further comprising one or more conductive traces disposed between and electrically connecting the TSV with the first elongate contact feature.

20. The bonded structure of claim 8 , wherein at least one of the first elongate contact feature and the second contact feature is curved.

Assignees

• Invensas Bonding Tech Inc

Inventors

• Enquist Paul M
• Fountain Jr Gaius Gillman
• Delacruz Javier A

Classifications

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title