Shift register and control method thereof

Patent metadata

Field	Value
Publication number	US-10269289-B2
Application number	US-201615375575-A
Country	US
Kind code	B2
Filing date	Dec 12, 2016
Priority date	Dec 23, 2015
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A shift register includes a control circuit, a switching circuit, a driving circuit, and a pull-down circuit. The control circuit is configured to output a control signal having a high level during a pull-up period and a voltage-regulating period respectively. The switching circuit is configured to provide a control voltage according to the control signal and a front stage signal outputted by a front x-stage shift register during the pull-up period. The driving circuit is configured to generate a driving signal according to the control voltage provided by the switching circuit, and output a home stage scan signal based on the driving signal. The pull-down circuit is configured to pull down a voltage level of the driving signal according to a scan signal outputted by a rear y-stage shift register during a pull-down period. The switching circuit is configured to regulate the driving signal and the home stage scan signal.

First claim

What is claimed is:

1. A shift register, comprising:
a control circuit configured to output a control signal having a high level during a pull-up period and a voltage-regulating period respectively;
a switching circuit coupled to the control circuit and configured to provide a control voltage in accordance with the control signal and a front stage signal outputted by a front x-stage shift register during the pull-up period;
a driving circuit coupled to the switching circuit and configured to receive the control voltage provided by the switching circuit, and to output a home stage scan signal in accordance with the control voltage; and
a pull-down circuit coupled to the driving circuit and configured to pull down a voltage level of the control voltage in accordance with a scan signal outputted by a rear y-stage shift register during a pull-down period;
wherein the switching circuit is configured to regulate the home stage scan signal in accordance with the control signal and the front stage signal outputted by the front x-stage shift register during the voltage-regulating period, and x, y are positive integers greater than or equal to 1.

2. The shift register of claim 1 , wherein the switching circuit is turned on in accordance with the control signal during the pull-up period, thereby charging the driving circuit by using the front stage signal having a high level to pull up a voltage level of the control voltage.

3. The shift register of claim 2 , wherein the control circuit outputs the control signal having a low level during a driving period, and the switching circuit is turned off in accordance with the control signal.

4. The shift register of claim 3 , wherein the driving circuit comprises:
a capacitor configured to store the control voltage; and
a first switch coupled to the capacitor and turned on in accordance with the control voltage during the driving period, so as to output the home stage scan signal in accordance with a high frequency clock signal.

5. The shift register of claim 4 , wherein the driving circuit further comprises:
a second switch comprising:
a first terminal configured to receive the high frequency clock signal;
a control terminal coupled to the capacitor and configured to receive the control voltage; and

a second terminal configured to output an actuating signal.

6. The shift register of claim 1 , wherein the pull-down circuit is turned on in accordance with the scan signal outputted by the rear y-stage shift register during the pull-down period, thereby grounding the driving circuit to pull down the voltage level of the control voltage.

7. The shift register of claim 4 , wherein the switching circuit comprises a third switch comprising:
a first terminal coupled to a terminal of the capacitor and configured to provide the control voltage;
a control terminal coupled to the control circuit and configured to receive the control signal; and
a second terminal configured to receive the front stage signal outputted by the front x-stage shift register, wherein the front stage signal is a front stage scan signal.

8. The shift register of claim 7 , wherein the switching circuit further comprises a fourth switch comprising:
a first terminal coupled to another terminal of the capacitor and an output terminal of the first switch;
a control terminal coupled to the control circuit and configured to receive the control signal; and
a second terminal coupled to a low voltage source.

9. The shift register of claim 5 , wherein the switching circuit comprises a third switch comprising:
a first terminal coupled to a terminal of the capacitor and configured to provide the control voltage;
a control terminal coupled to the control circuit and configured to receive the control signal; and
a second terminal configured to receive the front stage signal outputted by the front x-stage shift register, wherein the front stage signal is a front stage actuating signal.

10. The shift register of claim 9 , wherein the switching circuit further comprises a fourth switch comprising:
a first terminal coupled to another terminal of the capacitor and an output terminal of the first switch;
a control terminal coupled to the control circuit and configured to receive the control signal; and
a second terminal coupled to a low voltage source.

11. The shift register of claim 1 , wherein the control circuit comprises:
a pull-up unit configured to output the control signal having a high level in accordance with a front stage high frequency clock signal.

12. The shift register of claim 11 , wherein the control circuit comprises:
a pull-down unit configured to output the control signal having a low level in accordance with a rear stage driving signal of a rear z-stage shift register, wherein z is a positive integer greater than or equal to 1.

13. The shift register of claim 1 , wherein the front stage signal comprises one of a front stage scan signal and a front stage actuating signal.

14. A control method of a shift register, wherein the shift register comprises a control circuit, a switching circuit, a driving circuit and a pull-down circuit, and the switching circuit is coupled between the control circuit and the driving circuit, and the pull-down circuit is coupled to the driving circuit, wherein the control method comprises:
during a pull-up period, outputting a control signal having a high level by using the control circuit and providing a control voltage to the driving circuit by using the switching circuit in accordance with the control signal and a front stage signal outputted by a front x-stage shift register;
during a driving period, outputting a home stage scan signal by using the driving circuit in accordance with the control voltage;
during a pull-down period, pulling down a voltage level of the control voltage by using the pull-down circuit in accordance with a scan signal outputted by a rear y-stage shift register; and
during a voltage-regulating period, outputting the control signal having a high level by using the control circuit and regulating the home stage scan signal by using the switching circuit in accordance with the control signal and the front stage signal outputted by the front x-stage shift register, and x, y are positive integers greater than or equal to 1.

15. The control method of claim 14 , wherein during the pull-up period, the step of providing the control voltage by using the switching circuit in accordance with the control signal and the front stage signal outputted by the front x-stage shift register comprises:
during the pull-up period, charging the driving circuit by using the switching circuit in accordance with the control signal and the front stage signal to pull up a voltage level of the control voltage.

16. The control method of claim 14 , wherein during the pull-down period and the voltage-regulating period, the step of outputting the control signal having a high level by using the control circuit comprises:
during the pull-up period and the voltage-regulating period, outputting the control signal having a high level by using the control circuit in accordance with a front stage high frequency clock signal.

17. The control method of claim 14 , wherein during the pull-down period, the step of pulling down the voltage level of the control signal by using the pull-down circuit in accordance with the scan signal outputted by the rear y-stage shift register comprises:
during the pull-down period, grounding the driving circuit by using the pull-down circuit in accordance with the scan signal outputted by the rear y

Assignees

• Au Optronics Corp

Inventors

• Lin Wei-Li
• Tung Che-Wei
• Chen Yan-Ting

Classifications

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title