Forming an offset in an interdigitated capacitor of a microelectromechanical systems (MEMS) device

Patent metadata

Field	Value
Publication number	US-10266389-B2
Application number	US-201715664834-A
Country	US
Kind code	B2
Filing date	Jul 31, 2017
Priority date	Jul 31, 2017
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A method for forming a MEMS device may include performing a silicon-on-nothing process to form a cavity in a monocrystalline silicon substrate at a first depth relative to a top surface of the monocrystalline silicon substrate; forming, in an electrically conductive electrode region of the monocrystalline silicon substrate, an electrically insulated region extending to a second depth that is less than the first depth relative to the top surface of the monocrystalline silicon substrate; and etching the monocrystalline silicon substrate to expose a gap between a first electrode and a second electrode, wherein the second electrode is separated from the first electrode, within a first depth region, by a first distance defined by the electrically insulated region and the gap, and wherein the second electrode is separated from the first electrode, within a second depth region, by a second distance defined by the gap.

First claim

What is claimed is:

1. A method for forming a microelectromechanical system (MEMS) device, the method comprising:
performing a silicon-on-nothing process to form a cavity in a monocrystalline silicon substrate at a first depth relative to a top surface of the monocrystalline silicon substrate;
forming, in an electrically conductive electrode region of the monocrystalline silicon substrate and by performing a shallow trench isolation process, an electrically insulated region extending to a second depth that is less than the first depth relative to the top surface of the monocrystalline silicon substrate,
the electrically insulated region being a trench,
the trench being filled with a dielectric layer; and

etching the monocrystalline silicon substrate to expose a gap between a first electrode and a second electrode,
a first edge of the dielectric layer, an edge of the second electrode, and an edge of the cavity being approximately aligned,
the first edge of the dielectric layer being closer to the gap than a second edge of the dielectric layer,

the second electrode being separated from the first electrode, within a first depth region, by a first distance defined by the electrically insulated region and the gap,
the first depth region being vertically defined by a second distance equal to a vertical distance from the top surface to the second depth, and

the second electrode being separated from the first electrode, within a second depth region, by a third distance defined by the gap,
the second depth region being vertically defined by a fourth distance equal to a vertical distance from the first depth to the second depth.

2. The method of claim 1 , wherein the first electrode and the second electrode form part of an interdigitated capacitive electrode structure.

3. The method of claim 1 , wherein a readout based on the first electrode and the second electrode exhibits a linear relationship between capacitance and an offset of the first electrode and the second electrode due to deflection or rotation.

4. The method of claim 1 , wherein the first distance is greater than the third distance.

5. The method of claim 1 , wherein the second electrode is formed on a pillar that extends from a base of the cavity.

6. The method of claim 1 , wherein the first electrode is movable relative to the second electrode.

7. A method for forming an interdigitated capacitive electrode structure, the method comprising:
performing a silicon-on-nothing process to form a cavity in a substrate that includes at least one electrically conductive electrode region;
forming a structured electrode region such that a gap extending from a top surface of the substrate to the cavity is provided between a first electrode and a second electrode of the at least one electrically conductive electrode region,
wherein, to form an offset, at least a portion of an end surface of the second electrode is offset from an end surface of the first electrode relative to the top surface of the substrate; and

forming, in the structured electrode region and by performing a shallow trench isolation process, an electrically insulated region,
the electrically insulated region being a trench,
the trench being filled with a dielectric layer, and
a first edge of the dielectric layer closer to the gap, an edge of the second electrode, and an edge of the cavity being approximately aligned,
the first edge of the dielectric layer being closer to the gap than a second edge of the dielectric layer.

8. The method of claim 7 , wherein the end surface of the first electrode and the end surface of the second electrode face one another.

9. The method of claim 7 , wherein the cavity is formed at a first depth relative to the top surface of the substrate; and
wherein the electrically insulated region extends to a second depth that is less than the first depth relative to the top surface of the substrate.

10. The method of claim 9 , wherein the end surface of the first electrode is positioned closer than the cavity to the top surface of the substrate and the end surface of the second electrode is positioned farther than the electrically insulated region from the top surface of the substrate.

11. The method of claim 7 , wherein the first electrode is movable relative to the second electrode.

12. The method of claim 7 , wherein a readout based on the first electrode and the second electrode exhibits a linear relationship between capacitance and the offset due to deflection or rotation.

13. The method of claim 7 , wherein the second electrode is formed on a pillar that extends from a base of the cavity.

14. The method of claim 7 , wherein the end surface of the first electrode is positioned closer than the cavity to the top surface of the substrate and the end surface of the second electrode is positioned farther than the electrically insulated region from the top surface of the substrate.

15. A microelectromechanical system (MEMS) device, comprising:
a cavity formed in a monocrystalline silicon substrate at a first depth relative to a top surface of the monocrystalline silicon substrate;
an electrically insulated region, formed in an electrically conductive electrode region of the monocrystalline silicon substrate via a shallow trench isolation process, extending to a second depth that is less than the first depth relative to the top surface of the monocrystalline silicon substrate,
the electrically insulated region being a trench,
the trench being filled with a dielectric layer;

a first electrode;
a second electrode; and
a gap in the monocrystalline silicon substrate between the first electrode and the second electrode,
a first edge of the dielectric layer, an edge of the second electrode, and an edge of the cavity being approximately aligned,
the first edge of the dielectric layer being closer to the gap than a second edge of the dielectric layer,

the second electrode being separated from the first electrode, within a first depth region, by a first distance defined by the electrically insulated region and the gap,
the first depth region being vertically defined by a second distance equal to a vertical distance from the top surface to the second depth, and

the second electrode being separated from the first electrode, within a second depth region, by a third distance defined by the gap,
the second depth region being vertically defined by a fourth distance equal to a vertical distance from the first depth to the second depth.

16. The device of claim 15 , wherein the first electrode and the second electrode form part of an interdigitated capacitive electrode structure.

17. The device of claim 15 , wherein a readout based on the first electrode and the second electrode exhibits a linear relationship between capacitance and an offset of the first electrode and the second electrode due to deflection or rotation.

18. The device of claim 15 , wherein the first distance is greater than the third distance.

19. The device of claim 15 , wherein the second electrode is formed on a pillar that extends from a base of the cavity.

20. The device of claim 15 , wherein the first electrode is movable relative to the second electrode.

Assignees

• Infineon Technologies Dresden Gmbh

Inventors

• Pregl Sebastian
• Rudolph Uwe

Classifications

• B81C2201/013

  Etching · CPC title

• B81B3/0051 Primary

  For defining the movement, i.e. structures that guide or limit the movement of an element (mechanical arrangements for preventing or damping vibration or shock H01H3/60) · CPC title

• B81B2203/0315

  Cavities · CPC title

• B81B2201/0221

  Variable capacitors · CPC title

• B81B2203/04

  Electrodes · CPC title