Semiconductor device having vertical hall element

Patent metadata

Field	Value
Publication number	US-10263176-B2
Application number	US-201715808304-A
Country	US
Kind code	B2
Filing date	Nov 9, 2017
Priority date	Dec 5, 2016
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

A vertical Hall element having an improved sensitivity and reduced offset voltage includes: a second conductivity type semiconductor layer formed on a semiconductor substrate and having an impurity concentration that is distributed uniformly; a second conductivity type impurity diffusion layer formed on the semiconductor layer and having a concentration higher than in the semiconductor layer; a plurality of electrodes formed in a straight line on a surface of the impurity diffusion layer, and each formed from a second conductivity type impurity region that is higher in concentration than the impurity diffusion layer; and a plurality of first conductivity type electrode isolation diffusion layers each formed between two electrodes out of the plurality of electrodes on the surface of the impurity diffusion layer, to isolate the plurality of electrodes from one another.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type; and
a vertical Hall element on the semiconductor substrate,
the vertical Hall element comprising:
a semiconductor layer of a second conductivity type on the semiconductor substrate and having a uniformly distributed impurity concentration;
an impurity diffusion layer of the second conductivity type on the semiconductor layer and having a concentration of impurities higher than a concentration of impurities in the semiconductor layer;
a plurality of electrodes in a straight line on a surface of the impurity diffusion layer, each including an impurity region of the second conductivity type, where a concentration of impurities in the impurity region is higher than the concentration of impurities in the impurity diffusion layer; and
a plurality of electrode isolation diffusion layers of the first conductivity type, each between two adjacent electrodes among the plurality of electrodes on the surface of the impurity diffusion layer, and that isolate the plurality of electrodes from one another.

2. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type; and
a vertical Hall element on the semiconductor substrate,
the vertical Hall element comprising:
a semiconductor layer of a second conductivity type on the semiconductor substrate and having a uniformly distributed impurity concentration;
an impurity diffusion layer of the second conductivity type on the semiconductor layer and having a concentration of impurities higher than a concentration of impurities in the semiconductor layer;
a plurality of electrodes in a straight line on a surface of the impurity diffusion layer, each including an impurity region of the second conductivity type, where a concentration of impurities in the impurity region is higher than the concentration of impurities in the impurity diffusion layer; and
a plurality of electrode isolation diffusion layers of the first conductivity type, each between two adjacent electrodes among the plurality of electrodes on the surface of the impurity diffusion layer, and that isolate the plurality of electrodes from one another,
wherein a lowermost part of a depletion layer formed around each of the plurality of electrode isolation diffusion layers is positioned at substantially the same level as a top surface of the semiconductor layer.

3. A semiconductor device according to claim 1 , wherein the impurity diffusion layer has a concentration distribution in which the concentration decreases as a distance from the surface to the semiconductor layer increases.

4. A semiconductor device according to claim 2 , wherein the impurity diffusion layer has an impurity concentration distribution in which the concentration of impurities decreases as a distance from the top surface to the semiconductor layer increases.

5. A semiconductor device according to claim 1 , wherein the semiconductor layer and the impurity diffusion layer comprise an epitaxial layer.

6. A semiconductor device according to claim 2 , wherein the semiconductor layer and the impurity diffusion layer comprise an epitaxial layer.

7. A semiconductor device according to claim 3 , wherein the semiconductor layer and the impurity diffusion layer comprise an epitaxial layer.

8. A semiconductor device according to claim 4 , wherein the semiconductor layer and the impurity diffusion layer comprise an epitaxial layer.

9. A semiconductor device according to claim 1 , wherein the surface of the impurity diffusion layer and surfaces of the plurality of electrode isolation diffusion layers are covered with an insulating film, except for regions in which the plurality of electrodes reside.

10. A semiconductor device according to claim 2 , wherein the surface of the impurity diffusion layer and surfaces of the plurality of electrode isolation diffusion layers are covered with an insulating film, except for regions in which the plurality of electrodes reside.

11. A semiconductor device according to claim 5 , wherein the surface of the impurity diffusion layer and surfaces of the plurality of electrode isolation diffusion layers are covered with an insulating film, except for regions in which the plurality of electrodes reside.

12. A semiconductor device according to claim 6 , wherein the surface of the impurity diffusion layer and surfaces of the plurality of electrode isolation diffusion layers are covered with an insulating film, except for regions in which the plurality of electrodes reside.

13. A semiconductor device according to claim 1 , wherein a number of the plurality of electrodes is at least three.

14. A semiconductor device according to claim 2 , wherein the plurality of electrodes comprise at least three electrodes.

15. A semiconductor device according to claim 9 , wherein a number of the plurality of electrodes is at least three.

16. A semiconductor device according to claim 10 , wherein the plurality of electrodes comprise at least three electrodes.

17. A semiconductor device according to claim 1 , further comprising:
an element isolation diffusion layer of the first conductivity type, which encloses the vertical Hall element to electrically isolate the vertical Hall element from surroundings; and
an element forming region around the element isolation diffusion layer and having an element therein that is a constituent of one of a circuit configured to process an output signal from the vertical Hall element, and a circuit configured to supply a signal to the vertical Hall element,
wherein the element forming region comprises a well of the second conductivity type, and
wherein the well has a depth and a concentration distribution that are the same as a depth and concentration distribution of the impurity diffusion layer.

18. A semiconductor device according to claim 2 , further comprising:
an element isolation diffusion layer of the first conductivity type that encloses the vertical Hall element and electrically isolates the vertical Hall element from surrounding regions; and
an element forming region around the element isolation diffusion layer and configured to accommodate an element that is a constituent of one of: a circuit configured to process an output signal from the vertical Hall element; and a circuit configured to supply a signal to the vertical Hall element,
wherein the element forming region comprises a well of the second conductivity type, and
wherein the well has a depth and a concentration distribution that are the same as a depth and concentration distribution of the impurity diffusion layer.

19. A semiconductor device according to claim 13 , further comprising:
an element isolation diffusion layer of the first conductivity type, which encloses the vertical Hall element to electrically isolate the vertical Hall element from surroundings; and
an element forming region around the element isolation diffusion layer and having an element therein that is a constituent of one of a circuit configured to process an output signal from the vertical Hall element, and a circuit configured to supply a signal to the vertical Hall element,
wherein the element forming region comprises a well of the second conductivity type, and
wherein the well has a depth and a concentration distribution that are the same as a depth and concentration distribution of the impurity diffusion layer.

20. A semiconductor device according to claim 14 , further comprising:
an element isolation diffusio

Assignees

• Sii Semiconductor Corp
• Ablic Inc

Inventors

• Hioka Takaaki
• Ebihara Mika

Classifications

• H01L43/14

  Electricity · mapped topic

• H01L27/22

  Electricity · mapped topic

• H01L43/065 Primary

  Electricity · mapped topic

• H10N52/101 Primary

  Semiconductor Hall-effect devices · CPC title

• H10N50/85

  Materials of the active region · CPC title