Devices and methods for forming cross coupled contacts

Patent metadata

Field	Value
Publication number	US-10262941-B2
Application number	US-201615136384-A
Country	US
Kind code	B2
Filing date	Apr 22, 2016
Priority date	Apr 22, 2016
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

First claim

What is claimed is:

1. A method comprising:
obtaining an intermediate semiconductor device;
performing a first lithography to pattern a first shape for forming at least one first via opening;
performing a second lithography to pattern a second shape for forming at least one second via opening, wherein a portion of the second shape overlaps a portion of the first shape;
processing the first shape and the second shape to form an isolation region at the overlap separating the at least one first via opening and the at least one second via opening; and
forming four conductive regions in the at least one first and at least one second via openings.

2. The method of claim 1 , wherein the intermediate semiconductor device comprises:
a substrate;
an interlayer dielectric layer on the substrate;
a hard mask bi-layer on the interlayer dielectric layer;
a polysilicon layer on the hard mask bi-layer;
an etch stop layer on the polysilicon layer;
an oxide layer on the etch stop layer; and
a first lithography stack on the oxide layer.

3. The method of claim 2 , wherein performing the first lithography to pattern the first shape comprises:
using a first mask to form the at least one first via opening, wherein using the first mask to form the at least one first via opening comprises:
exposing the first mask to form at least one first via pattern in the first lithography stack;
etching the oxide layer to form the at least one first via opening; and
stripping the first lithography stack from the intermediate semiconductor device.

4. The method of claim 1 , wherein the intermediate semiconductor device comprises:
a substrate;
an interlayer dielectric layer on the substrate;
a hard mask bi-layer on the interlayer dielectric layer;
a polysilicon layer on the hard mask bi-layer;
an etch stop layer on the polysilicon layer;
an oxide layer on the etch stop layer; and
a second lithography stack on the oxide layer.

5. The method of claim 4 , wherein performing a second lithography to pattern a second shape overlapping a portion of the first shape comprises:
performing a second lithography using a second mask to form the at least one second via opening, wherein the at least one second via opening overlaps at least one first via opening, wherein performing the second lithography using the second mask to form the at least one second via opening comprises:
exposing the second mask to form at least one second via pattern in the second lithography stack;
etching the oxide layer to form the at least one second via opening; and
stripping the second lithography stack from the intermediate semiconductor device.

6. The method of claim 5 , wherein performing the second lithography using the second mask to form the at least one second via opening further comprises:
performing a developing process to expose a self-aligned block where the at least one first via opening overlaps the at least one second via pattern;
etching the intermediate semiconductor device to expose the polysilicon layer of the self-aligned block; and
performing a wet etch to enlarge the separation between the at least one first via opening and the at least one second via pattern to form recesses in the etch stop layer.

7. The method of claim 6 , wherein the wet etch to form the recesses is a hot phosphoric nitride wet etch.

8. The method of claim 7 , wherein forming four conductive regions separated by the isolation region comprises:
forming at least four contacts from the at least one first via opening and the at least one second via opening, wherein forming the at least four contacts comprises:
performing an oxidation to form a hard mask layer on the self-aligned block;
performing a first etch to remove a portion of the etch stop layer and expose a portion the polysilicon layer in the at least one first via opening and the at least one second via opening; and
performing a second etch to remove a portion of the polysilicon layer and expose a portion of the hard mask bi-layer.

9. The method of claim 8 , wherein forming the at least four contacts from the at least one first via opening and the at least one second via opening further comprises:
depositing a spacer layer over the intermediate semiconductor device; and
etching the spacer layer to form sidewall spacers in the at least one first via opening and the at least one second via opening.

10. The method of claim 9 , wherein forming the at least four contacts from the at least one first via opening and the at least one second via opening further comprises:
performing a dry etch to remove a portion of a second hard mask layer of the hard mask bi-layer in the at least one first via opening and the at least one second via opening;
performing an isotropic etch to remove the sidewall spacers in the at least one first via opening and the at least one second via opening and to remove the hard mask layer on the self-aligned block to expose a self-aligned polysilicon block; and
performing an etch to remove a portion of the first hard mask layer of the hard mask bi-layer in the at least one first via opening and the at least one second via opening.

11. The method of claim 10 , wherein forming the at least four contacts from the at least one first via opening and the at least one second via opening further comprises:
performing an etch to remove a portion of the interlayer dielectric layer in the at least one first via opening and the at least one second via opening to form at least one first contact trench and at least one second contact trench; and
performing an etch to remove the polysilicon layer from the intermediate semiconductor device.

12. The method of claim 11 , wherein forming the at least four contacts from the at least one first via opening and the at least one second via opening further comprises:
depositing a barrier layer over the intermediate semiconductor device and into the at least one first contact trench and at least one second contact trench;
performing a metal fill process to deposit a metal layer on the intermediate semiconductor device and into the at least one first contact trench and at least one second contact trench; and
performing planarization to remove excess metal layer, excess barrier layer, and the hard mask bi-layer to form at least two first contacts and at least two second contacts.

13. The method of claim 1 , wherein the isolation region forms an electrical separation between the four conductive regions, and wherein ends of the at least one first via opening are positioned adjacent to ends of the at least one second via opening and the isolation region is positioned to separate the ends of the at least one first via opening from the ends of the at least one second via opening.

Assignees

• Globalfoundries Inc

Inventors

• Bouche Guillaume
• Stephens Jason Eugene
• Guha Neogi Tuhin
• Sun Kai
• Civay Deniz Elizabeth
• PRITCHARD David Charles
• Wei Andy

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title