Three plate MIM capacitor via integrity verification

Patent metadata

Field	Value
Publication number	US-10262934-B2
Application number	US-201715800106-A
Country	US
Kind code	B2
Filing date	Nov 1, 2017
Priority date	Feb 7, 2017
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

A three plate MIM capacitor structure includes a three plate MIM capacitor, a first wire in a metal layer above/below the three plate MIM, a second wire below/above the three plate MIM, a third wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first wire and the second and third wires or detecting leakage current across the second wire and the third wire.

First claim

The invention claimed is:

1. A method of testing a three plate MIM capacitor structure comprising:
applying a voltage to a first plate of a three plate MIM capacitor, a second plate of the three plate MIM capacitor, and a third plate of the three plate MIM capacitor;
applying ground potential to a via adjacent to the three plate MIM capacitor;
detecting leakage current across the middle plate and the via, detecting leakage current across the top plate and the via, or detecting leakage current across the middle plate and the via; and
determining there is a short between one of the bottom plate, middle plate, or top plate and the via caused by a defect of the via, if leakage current is detected across the middle plate and the via, if leakage current is detected across the top plate and the via, or if leakage current is detected across the middle plate and the via.

2. The method of claim 1 , wherein a first via is connected to the middle plate and extends through an associated clearance of the top plate.

3. The method of claim 2 , wherein a second via is connected to both the top plate and the bottom plate and extends through an associated clearance of the middle plate.

4. The method of claim 3 , wherein a first wire is connected to the via and is serpentine shaped traversing the three plate MIM capacitor.

5. The method of claim 4 , wherein a second wire is connected to the second via, wherein a third wire is connected to the third via, and wherein the second wire and the third wire comprises two parallel portions connected by an orthogonal portion.

6. The method of claim 5 , wherein one of the two parallel portions of the third wire is between the two parallel portions of the second wire.

7. The method of claim 4 , wherein the first wire is located in a wiring level above or below the three plate MIM capacitor.

8. A three plate MIM capacitor structure comprising:
a three plate MIM capacitor comprising a bottom plate, a middle plate, and a top plate;
a via matrix normal to the bottom plate, the middle plate, and the top plate, the via matrix comprising: a first via group comprising vias that are adjacent to the bottom plate, middle plate, and top plate; a second via group comprising vias that are configured to contact only the middle plate; and a third via group comprising vias that are configured to contact only the top plate and bottom plate;
a first wire within a wiring level below the three plate MIM capacitor connected to the first via group;
a second wire within a wiring level above the three plate MIM capacitor connected to the second via group; and
a third wire within a wiring level above the three plate MIM capacitor connected to the third via group.

9. The three plate MIM capacitor structure of claim 8 , wherein the vias of the first via group are comprised within a first column of the via matrix, the vias of the second via group are comprised within a second column of the via matrix, and the vias of the third via group are comprised within a third column of the via matrix.

10. The three plate MIM capacitor structure of claim 8 , wherein the vias of the first via group are comprised within a first row of the via matrix, the vias of the second via group are comprised within a second row of the via matrix, and the vias of the third via group are comprised within a third row of the via matrix.

11. The three plate MIM capacitor structure of claim 8 , wherein the vias of the first via group are comprised within a first diagonal of the via matrix, the vias of the second via group are comprised within a second diagonal of the via matrix, and the vias of the third via group are comprised within a third diagonal of the via matrix.

12. The three plate MIM capacitor structure of claim 8 , wherein the vias of the second via group extend through associated clearances within the top plate.

13. The three plate MIM capacitor structure of claim 8 , wherein the vias of the third via group extend through associated clearances within the middle plate.

14. The three plate MIM capacitor structure of claim 8 , wherein the first wire is serpentine shaped.

15. The three plate MIM capacitor structure of claim 8 , wherein each of the second wire and third wire comprises two parallel portions connected by an orthogonal portion.

16. The three plate MIM capacitor structure of claim 15 , wherein one of the two parallel portions of the third wire is between the two parallel portions of the second wire.

17. A three plate MIM capacitor structure comprising:
a three plate MIM capacitor comprising a bottom plate, a middle plate, and a top plate;
a via matrix normal to the bottom plate, the middle plate, and the top plate, the via matrix comprising: a first via group comprising vias that are adjacent to the bottom plate, middle plate, and top plate; a second via group comprising vias that are configured to contact only the middle plate; and a third via group comprising vias that are configured to contact only the top plate and bottom plate;
a first wire within a wiring level above the three plate MIM capacitor connected to the first via group;
a second wire within a wiring level below the three plate MIM capacitor connected to the second via group; and
a third wire within a wiring level below the three plate MIM capacitor connected to the third via group.

18. The three plate MIM capacitor structure of claim 17 , wherein the vias of the first via group are comprised within a first column of the via matrix, the vias of the second via group are comprised within a second column of the via matrix, and the vias of the third via group are comprised within a third column of the via matrix.

19. The three plate MIM capacitor structure of claim 17 , wherein the vias of the first via group are comprised within a first row of the via matrix, the vias of the second via group are comprised within a second row of the via matrix, and the vias of the third via group are comprised within a third row of the via matrix.

20. The three plate MIM capacitor structure of claim 17 , wherein the vias of the first via group are comprised within a first diagonal of the via matrix, the vias of the second via group are comprised within a second diagonal of the via matrix, and the vias of the third via group are comprised within a third diagonal of the via matrix.

Assignees

• IBM

Inventors

• Kim Andrew T
• Li Baozhen
• Linder Barry P
• Wu Ernest Y

Classifications

• G01R31/64

  Testing of capacitors · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title