Planarization method

Patent metadata

Field	Value
Publication number	US-10262869-B2
Application number	US-201815904405-A
Country	US
Kind code	B2
Filing date	Feb 25, 2018
Priority date	Mar 24, 2017
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.

First claim

What is claimed is:

1. A planarization method, comprising:
providing a substrate having a semiconductor structure formed thereon;
forming a dielectric layer covering the substrate and the semiconductor structure, wherein a portion of the dielectric layer covering the semiconductor structure has a first top surface, the other portion of the dielectric layer not covering the semiconductor structure has a second top surface;
forming a mask layer on the dielectric layer;
performing a first chemical mechanical polishing process to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer;
performing an etching process to anisotropically remove a portion of the dielectric layer from the opening until obtaining a third top surface of the dielectric layer;
removing the mask layer; and
performing a second chemical mechanical polishing process.

2. The planarization method according to claim 1 , wherein the etching process is a wet etching process.

3. The planarization method according to claim 1 , wherein the semiconductor structure is not exposed from the third top surface.

4. The planarization method according to claim 1 , wherein the third top surface has an area larger than an area of the opening.

5. The planarization method according to claim 1 , wherein a tip portion of the mask layer protrudes and suspends from a perimeter of the third top surface after the etching process.

6. The planarization method according to claim 1 , wherein the first top surface is higher than the second top surface and the second top surface is higher than a top surface of the semiconductor structure.

7. The planarization method according to claim 6 , wherein the third top surface is higher than the second top surface.

8. The planarization method according to claim 6 , wherein the third top surface is lower than the second top surface.

9. The planarization method according to claim 1 , wherein the first top surface is higher than the second top surface and the second top surface is lower than a top surface of the semiconductor structure.

10. The planarization method according to claim 9 , wherein a cap layer is formed on the dielectric layer after removing the mask layer and before performing the second polishing process.

11. The planarization method according to claim 1 , wherein a removal process is performed to remove the mask layer.

12. The planarization method according to claim 1 , wherein the mask layer is removed by the second planarization process.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Lin Jen-Chieh
• Chen Lee-Yuan
• Lin Wen-Chin
• Huang Chi-Lune
• Chuang Pi-Hung
• Chen Tai-Lin
• Chen Sun-Hong

Classifications

• H10P95/066

  the removal being a selective chemical etching step, e.g. selective dry etching through a mask · CPC title

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W20/092

  by smoothing the dielectric parts · CPC title