System on a chip with fast wake from sleep

Patent metadata

Field	Value
Publication number	US-9778728-B2
Application number	US-201414289775-A
Country	US
Kind code	B2
Filing date	May 29, 2014
Priority date	May 29, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

First claim

What is claimed is:

1. An integrated circuit comprising:
at least one processor forming a central processing unit (CPU) in the integrated circuit; and
a plurality of components, wherein the plurality of components includes a first component coupled to the CPU, wherein the first component is configured to remain powered while the CPU and other ones of the plurality of components are powered off, and wherein the first component is configured to cause the CPU and the other ones of the plurality of components to power up, and the first component is configured to program at least a portion of the other ones of the plurality of components with configuration data stored in the first component, and the first component is configured to release the at least one processor from reset to execute kernel code when a state of the plurality of components is prepared for kernel code execution subsequent to the plurality of components being programmed with the configuration data by the first component, and wherein releasing the at least one processor from reset to execute kernel code includes bypassing an execution of read-only memory (ROM) load code and boot code responsive to programming at least the portion of the other ones of the plurality of components, wherein the ROM load code and the boot code is not executed between a determination that the CPU and the other ones of the plurality of components are to be powered up and the release of the at least one processor to execute the kernel code, and wherein the kernel code is a core of an operating system and manages resources in a system that includes the integrated circuit for use by application programs executed by the processors, and wherein a second one of the plurality of components is a memory controller coupled to a memory during use, and wherein the CPU is configured to store state corresponding to the other ones of the plurality of components in the memory prior to the other ones of the plurality of components and the CPU powering down, and wherein the configuration data stored in the first component matches a portion of the state stored in the memory, wherein the first component is configured to determine that the CPU and the other ones of the plurality of components are to be powered up by collecting N sensor samples from one or more sensors coupled to the integrated circuit during use, wherein N is a positive integer, and wherein the first component is configured to filter the N sensor samples to detect an attribute of the N sensor samples, and wherein the first component determines that the CPU and the other ones of the plurality of components are to be powered up responsive to detecting the attribute in the N sensor samples.

2. The integrated circuit as recited in claim 1 wherein the first component comprises a second processor configured to determine that the CPU and the other ones of the plurality of components are to be powered up.

3. The integrated circuit as recited in claim 2 wherein the second processor is configured to determine that the CPU and the other ones of the plurality of components are to be powered up responsive to executing code stored in the first component.

4. The integrated circuit as recited in claim 3 wherein the second processor is configured to predict that the CPU and the other ones of the plurality of components are to be powered up, and wherein the CPU executing the kernel code is configured to verify the prediction and continue processing or power back down based on a result of verifying the prediction.

5. The integrated circuit as recited in claim 1 wherein the attribute is a pattern in the data across the N sensor samples.

6. The integrated circuit as recited in claim 1 wherein the first component is configured to collect each respective sensor sample of the N sensor samples at a respective one of N different points in time, wherein the first component is configured to predict that the CPU and the other ones of the plurality of components will be powered up responsive to N second sensor samples to be collected from the one or more sensors subsequent to the N sensor samples from the one or more sensors being filtered, wherein the N second sensor samples are detected by the one or more sensors subsequent in time to the N sensor samples and are collected from the one or more sensors subsequent in time to the N sensor samples, and wherein each respective second sensor sample of the N second sensor samples is collected at a respective one of N different second points in time, and wherein the N second sensor samples are collected from a same set of the one or more sensors from which the N sensor samples are collected, and wherein the first component is configured to cause the CPU and the other ones of the plurality of components to power up responsive to the prediction, and wherein the first component is configured to verify the prediction responsive to the N second sensor samples.

7. A method comprising:
in a system on a chip (SOC) that includes at least one processor forming a central processing unit (CPU) in the SOC and further including a plurality of components, wherein the plurality of components include a first component that remains powered during use when other ones of the plurality of components and the CPU are powered down, collecting N sensor samples by the first component from one or more sensors coupled to the SOC during use, wherein N is a positive integer;
filtering the N sensor samples in the first component to detect an attribute of the N sensor samples;
determining in the first component that the CPU and the plurality of components are to be powered up responsive to detecting the attribute in the N sensor samples;
powering up the other ones of the plurality of components and the CPU responsive to the determining;
programming a configuration of at least a portion of the other ones of the plurality of components and the CPU responsive to powering up the other ones of the plurality of components and the CPU, wherein the programming is performed by the first component using data stored in the first component, wherein a configuration of each of the other ones of the plurality of components and the CPU is stored in a memory to which the SOC is coupled during use, and wherein the configuration stored in the first component matches a corresponding subset of the configuration stored in the memory; and
releasing the CPU from reset to execute kernel code when a state of the plurality of components is prepared for kernel code execution subsequent to the plurality of components being programmed with the configuration data by the first component, wherein releasing the processor from reset to execute kernel code comprises bypassing an execution of read-only memory (ROM) load code and boot code responsive to programming the configuration of at least the portion of the other ones of the plurality of components, wherein the ROM load code and the boot code is not executed between determining that the CPU and the plurality of components are to be powered up and the release of the at least one processor to execute the kernel code, and wherein the kernel code is a core of an operating system and manages resources in a system that includes the SOC for use by application programs executed by CPU, and wherein releasing the CPU from reset is performed by the first component.

8. The method as recited in claim 7 wherein the determining is responsive to predicting that the other ones of the plurality of components and the CPU are to be powered up, wherein the method further comprises verifying an accuracy of the prediction.

9. The method as recited in claim 8 wherein the verifying comprises determining that the prediction is inaccurate, and the method further comprises powering down

Assignees

• Apple Inc

Inventors

• Dalal Anand
• De Cesare Joshua P

Classifications

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/3231

  Monitoring the presence, absence or movement of users · CPC title

• G06F1/3215

  Monitoring of peripheral devices · CPC title

• G06F1/3209

  Monitoring remote activity, e.g. over telephone lines or network connections · CPC title