Separate clock synchronous architecture

Patent metadata

Field	Value
Publication number	US-10261539-B2
Application number	US-201715475328-A
Country	US
Kind code	B2
Filing date	Mar 31, 2017
Priority date	Mar 31, 2017
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.

First claim

The invention claimed is:

1. An apparatus comprising:
a plurality of independently clocked devices, each having a respective local clock generator, wherein each of said respective local clock generators comprises (i) a reference clock generator configured to generate a local reference clock signal in response to a control signal and (ii) a synchronization control circuit configured to generate said control signal in response to said local reference clock signal and a low frequency synchronization signal; and
a low frequency beacon, said low frequency beacon communicating said low frequency synchronization signal to each of said independently clocked devices, wherein said respective local clock generators of said plurality of independently clocked devices are synchronized using said low frequency synchronization signal.

2. The apparatus according to claim 1 , wherein said low frequency synchronization signal is generated by one of said plurality of independently clocked devices configured as said low frequency beacon, and distributed to each of the other independently clocked devices.

3. The apparatus according to claim 2 , wherein said low frequency synchronization signal is distributed wirelessly.

4. The apparatus according to claim 1 , wherein each of said independently clocked devices is separated in space from the others.

5. The apparatus according to claim 1 , wherein said low frequency beacon is located on a motherboard and each of said independently clocked devices is located on a peripheral board.

6. The apparatus according to claim 5 , wherein each of said peripheral boards is connected to said motherboard by a backplane connector.

7. The apparatus according to claim 5 , wherein each of said peripheral boards is connected to said motherboard by a serial communication bus.

8. The apparatus according to claim 5 , wherein each of said peripheral boards is connected to said motherboard by a peripheral component interconnect express bus.

9. The apparatus according to claim 1 , wherein each of said respective local clock generators is configured to generate a local high speed clock signal.

10. The apparatus according to claim 9 , wherein each of said respective local clock generators further comprises:
a frequency synthesizer configured to generate said local high speed clock signal.

11. The apparatus according to claim 1 , wherein each of said respective local clock generators is configured to generate a local high speed spread spectrum clock signal.

12. The apparatus according to claim 11 , wherein each of said respective local clock generators is configured to modulate a spread of said spread spectrum clock signal based on said low frequency synchronization signal.

13. A method of synchronizing a plurality of independently clocked devices comprising:
configuring one of said plurality of independently clocked devices as a beacon device comprising a master clock and generating a low frequency synchronization signal using a respective clock generator of the beacon device;
distributing the low frequency synchronization signal to remaining ones of the plurality of independently clocked devices; and
synchronizing respective clock generators of the remaining ones of the plurality of independently clocked devices with the beacon device using the low frequency synchronization signal, wherein each of the respective clock generators of the remaining ones of the plurality of independently clocked devices comprises (i) a reference clock generator configured to generate a local reference clock signal in response to a control signal and (ii) a synchronization control circuit configured to generate the control signal in response to the local reference clock signal and the low frequency synchronization signal.

14. The method according to claim 13 , wherein said low frequency synchronization signal is distributed wirelessly.

15. The method according to claim 13 , wherein each of said independently clocked devices is separated in space from the others.

16. A separate clock synchronous architecture comprising:
a low frequency beacon configured to generate a low frequency synchronization signal; and
a distribution network configured to communicate said low frequency synchronization signal to a plurality of independently clocked devices, wherein (i) each of said plurality of independently clocked devices comprises a respective local clock generator and (ii) each of said respective local clock generators comprises a reference clock generator configured to generate a local reference clock signal in response to a control signal and a synchronization control circuit configured to generate said control signal in response to said local reference clock signal and said low frequency synchronization signal, such that said respective clock generators of said plurality of independently clocked devices are synchronized to one another using the low frequency synchronization signal.

17. The separate clock synchronous architecture according to claim 16 , wherein said low frequency synchronization signal is distributed wirelessly.

18. The separate clock synchronous architecture according to claim 16 , wherein each of said independently clocked devices is separated in space from the others.

19. The separate clock synchronous architecture according to claim 16 , wherein each of said respective clock generators is configured to generate a local high speed spread spectrum clock signal.

20. The separate clock synchronous architecture according to claim 19 , wherein each of said respective clock generators is configured to modulate a spread of said spread spectrum clock signal based on said low frequency synchronization signal.

Assignees

• Integrated Device Tech

Inventors

• Bal Jagdeep
• Wade Ron

Classifications

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F13/4291

  using a clocked protocol · CPC title