Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface

US10256365B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10256365-B2
Application numberUS-201815948593-A
CountryUS
Kind codeB2
Filing dateApr 9, 2018
Priority dateApr 13, 2017
Publication dateApr 9, 2019
Grant dateApr 9, 2019

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Abstract

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A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.

First claim

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The invention claimed is: 1. A method of forming an electrical device comprising: epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a substrate that is first textured, the first conductivity type semiconductor material continuously extending along an entirety of the substrate in a plurality of triangular shaped islands; conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands for a second textured surface of a photovoltaic device; and forming a light emitting diode on the second textured surface of the photovoltaic device. 2. The method of claim 1 , wherein the first textured surface comprises a plurality of islands of triangular geometry. 3. The method of claim 1 , wherein the substrate is comprised of silicon, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is gallium nitride. 4. The method of claim 1 , wherein the substrate is comprised of sapphire, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is gallium nitride. 5. The method of claim 1 , wherein the substrate is comprised of silicon, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum gallium nitride. 6. The method of claim 1 , wherein the substrate is comprised of sapphire, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum gallium nitride. 7. The method of claim 1 , wherein the substrate is comprised of silicon, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum nitride. 8. The method of claim 1 , wherein the substrate is comprised of sapphire, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum nitride. 9. A method of forming an electrical device comprising: forming a substrate having a first textured surface of a first plurality of triangular shaped peaks; forming a second textured surface on the substrate, the second textured surface including a second plurality of triangular shaped peaks; conformally forming a first conductivity type III-V semiconductor material on the second textured surface of the substrate; conformally forming a second conductivity type III-V semiconductor material on the first conductivity type III-V semiconductor material to produce a third textured surface for a photovoltaic device; and forming a light emitting diode on the third textured surface of the photovoltaic device. 10. The method of claim 9 , wherein the substrate is comprised of silicon, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is gallium nitride. 11. The method of claim 9 , wherein the substrate is comprised of sapphire, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is gallium nitride. 12. The method of claim 9 , wherein the substrate is comprised of silicon, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum gallium nitride. 13. The method of claim 9 , wherein the substrate is comprised of sapphire, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum gallium nitride. 14. The method of claim 9 , wherein the substrate is comprised of silicon, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum nitride. 15. The method of claim 9 , wherein the substrate is comprised of sapphire, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum nitride. 16. A electrical device comprising: a first type III-V semiconductor material having a first conductivity type for a junction of a photovoltaic device in direct contact with a textured surface of the semiconductor substrate, the first type III-V semiconductor material having the first conductivity type is a continuous layer of triangular geometry islands that are in contact end to end that is present on correspondingly textured surface of the substrate; a conformal layer of second type III-V semiconductor material having a second conductivity for the junction of the photovoltaic device is in direct contact with the first type III-V semiconductor material to provide a p-n junction, wherein the conformal layer over the continuous layer of triangular geometry islands provides a textured light receiving surface for the photovoltaic device; and a light emitting diode present on the textured surface of the photovoltaic device. 17. The electrical device of claim 16 , wherein the textured surface of the substrate comprises a plurality of islands of triangular geometry. 18. The electrical device of claim 16 , wherein the substrate is comprised of silicon, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is gallium nitride, or the substrate is comprised of sapphire, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is gallium nitride. 19. The electrical device of claim 16 , wherein the substrate is comprised of silicon, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum gallium nitride, or the substrate is comprised of sapphire, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum gallium nitride. 20. The electrical device of claim 19 , wherein the substrate is comprised of silicon, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum nitride, or the substrate is comprised of sapphire, the first conductivity type is n-type, the second conductivity type is p-type and the type III-V semiconductor material layer is aluminum nitride.

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What does patent US10256365B2 cover?
A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01L33/007. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 09 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).