Method for manufacturing a semiconductor device where a plurality of layers including a semiconductor layer made of an oxide semiconductor are stacked to form a thin film transistor

Patent metadata

Field	Value
Publication number	US-10256346-B2
Application number	US-201515516434-A
Country	US
Kind code	B2
Filing date	Oct 1, 2015
Priority date	Oct 8, 2014
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device ( 100 ) where a passivation film ( 17 ) is to be formed at an upper layer of a semiconductor layer ( 11 ) made of an oxide semiconductor, deposition conditions of the passivation film ( 17 ) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer ( 11 )) at an interface of the semiconductor layer ( 11 ) to the passivation film ( 17 ) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer ( 11 ).

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor device where a plurality of layers including a semiconductor layer made of an oxide semiconductor are stacked so as to form a thin film transistor, the method comprising:
a semiconductor layer formation step of forming the semiconductor layer; and
an upper layer formation step of forming an upper layer of the semiconductor layer,
wherein, in the upper layer formation step, the upper layer is deposited in such a way that, in the semiconductor layer, a proportion of pure metal indicating a ratio of pure metal to all components of the oxide semiconductor is higher at an interface of the semiconductor layer to the upper layer than in a bulk.

2. The method for manufacturing according to claim 1 , wherein, in the upper layer formation step, the upper layer is deposited in such a way that the proportion of pure metal at a peripheral edge portion, of a pattern of the semiconductor layer, of the interface is higher than the proportion of pure metal in the bulk.

3. The method for manufacturing according to claim 1 , wherein, in the upper layer formation step, the upper layer is deposited in such a way that the proportion of pure metal at an upper surface portion, of a pattern of the semiconductor layer, of the interface is higher than the proportion of pure metal in the bulk.

4. The method for manufacturing according to claim 1 , wherein, in the upper layer formation step, the upper layer is deposited in such a way that both the proportion of pure metal at a peripheral edge portion, of a pattern of the semiconductor layer, of the interface and the proportion of pure metal at an upper surface portion, of the pattern of the semiconductor layer, of the interface are higher than the proportion of pure metal in the bulk.

5. The method for manufacturing according to claim 1 , wherein, in the upper layer formation step, a passivation film is formed as the upper layer of the semiconductor layer.

6. The method for manufacturing according to claim 1 , wherein, in the upper layer formation step, an insulating film for insulating a gate electrode of the thin film transistor and the semiconductor layer from each other is formed as the upper layer of the semiconductor layer.

7. The method for manufacturing according to claim 1 , wherein the upper layer of the semiconductor layer is formed from a silicon dioxide film.

8. The method for manufacturing according to claim 7 , wherein, in the upper layer formation step, deposition temperature for depositing the silicon dioxide film is set to 150 degrees or higher and 250 degrees or lower.

9. The method for manufacturing according to claim 7 , wherein, in the upper layer formation step, deposition power for depositing the silicon dioxide film is set to at least 800 W.

10. The method for manufacturing according to claim 7 , wherein, in the upper layer formation step, baking temperature for performing baking process on the silicon dioxide film is set to 250 degrees or higher and 350 degrees or lower.

Assignees

• Sharp Kk

Inventors

• Saitoh Takao
• Kanzaki Yohsuke
• Takamaru Yutaka
• Ide Keisuke
• Kaneko Seiji

Classifications

• H01L29/786

  Electricity · mapped topic

• C23C16/42

  Silicides · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L29/78618

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic