Semiconductor device having multiple gate pads

Patent metadata

Field	Value
Publication number	US-10256227-B2
Application number	US-201615097024-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Apr 12, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

Disclosed are semiconductor devices that include additional gate pads, and methods of fabricating and testing such devices. A device may include a first gate pad, a second gate pad, and a third gate pad. The first gate pad is connected to a gate including a gate oxide layer. The second and third gate pads are part of an electro-static discharge (ESD) protection network for the device. The ESD protection network is initially isolated from the first gate pad and hence from the gate and gate oxide layer. Accordingly, gate oxide integrity (GOI) testing can be effectively performed and the reliability and quality of the gate oxide layer can be checked. The second gate pad can be subsequently connected to the first gate pad to enable the ESD protection network, and the third gate pad can be subsequently connected to an external terminal when the device is packaged.

First claim

What is claimed is:

1. A method of gate oxide integrity (GOI) testing for semiconductor devices, the method comprising:
with the semiconductor devices on a wafer, during the GOI testing, applying a first voltage to a first gate pad of a semiconductor device of the semiconductor devices, the semiconductor device further comprising a gate comprising a gate oxide layer, wherein the first voltage is greater than the rated operational voltage of the gate oxide layer, the semiconductor device also comprising a second gate pad and a third gate pad that are electrically isolated from the first gate pad at all times during the GOI testing, wherein the second gate pad and the third gate pad comprise a portion of an electro-static discharge (ESD) protection network for the semiconductor device, wherein the ESD protection network is electrically isolated from the first gate pad and the first voltage during the GOI testing, wherein the first gate pad occupies less area of the semiconductor device than the third gate pad, and wherein the second gate pad occupies less area of the semiconductor device than the third gate pad;
after completion of the GOI testing, removing the first voltage from the first gate pad; and
after said removing, forming a first electrical connection between the first gate pad and the second gate pad to enable the ESD protection network and to also enable a connection between the gate of the semiconductor device and a terminal that is external to the semiconductor device.

2. The method of claim 1 , further comprising applying a second voltage to the ESD protection network after the first voltage is removed from the first gate pad and before the first electrical connection between the first gate pad and the second gate pad is formed.

3. The method of claim 1 , wherein the ESD protection network is selected from the group consisting of: a two-stage ESD network comprising a resistor and at least two Zener diodes; and a one-stage ESD network comprising a Zener diode.

4. The method of claim 1 , further comprising:
separating the semiconductor device from the wafer; and
forming a second electrical connection between the third gate pad and the terminal that is external to the semiconductor device.

5. The method of claim 4 , further comprising testing the semiconductor device after the second electrical connection between the third gate pad and the terminal is formed.

6. The method of claim 1 , wherein the semiconductor device comprises a vertical device comprising a metal-oxide-semiconductor field-effect transistor (MOSFET).

7. A method of gate oxide integrity (GOI) testing and electro-static discharge (ESD) protection network testing for semiconductor devices, the method comprising:
with the semiconductor devices on a wafer, performing the GOI testing by applying a first voltage to a first gate pad of a semiconductor device of the semiconductor devices, the semiconductor device further comprising a gate comprising a gate oxide layer, wherein the first voltage is greater than the rated operational voltage of the gate oxide layer, the semiconductor device also comprising a second gate pad and a third gate pad that are electrically isolated from the first gate pad at all times during the GOI testing when the first voltage is applied to the first gate pad, wherein the second and third gate pads comprise a portion of the ESD protection network and wherein the first gate pad occupies less area of the semiconductor device than the third gate pad, wherein the ESD protection network is electrically isolated from the first gate pad and the first voltage during the GOI testing, and wherein the second gate pad occupies less area of the semiconductor device than the third gate pad;
after completion of the GOI testing, removing the first voltage from the first gate pad; and
after completion of the GOI testing and before an electrical connection between the first gate pad and the ESD protection network is formed, testing the ESD protection network, wherein said testing the ESD protection network comprises applying a second voltage to the ESD protection network, wherein the second gate pad and the third gate pad are electrically isolated from the first gate pad at all times during the testing of the ESD protection network.

8. The method of claim 7 , further comprising, after said removing, forming a first electrical connection between the first gate pad and the second gate pad to enable the ESD protection network and to also enable a connection between the pate of the semiconductor device and a terminal that is external to the semiconductor device.

9. The method of claim 7 , wherein the ESD protection network is selected from the group consisting of: a two-stage ESD network comprising a resistor and at least two Zener diodes; and a one-stage ESD network comprising a Zener diode.

10. The method of claim 7 , further comprising:
separating the semiconductor device from the wafer; and
after said separating, forming a second electrical connection between the third gate pad and a terminal that is external to the semiconductor device.

11. The method of claim 10 , further comprising testing the semiconductor device after the second electrical connection between the third gate pad and the terminal is formed.

12. The method of claim 7 , wherein the semiconductor device comprises a vertical device comprising a metal-oxide-semiconductor field-effect transistor (MOSFET).

Assignees

• Vishay Siliconix

Inventors

• Park Chanho
• Shibib Ayman
• Terrill Kyle

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5453

  connecting between multiple bond pads on a chip, e.g. daisy chain · CPC title

• H10W72/019

  of bond pads · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title