Separation of integrated circuit structure from adjacent chip

Patent metadata

Field	Value
Publication number	US-10256204-B2
Application number	US-201615345608-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Nov 8, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a semiconductor region including an interconnect pad positioned on an upper surface thereof, the interconnect pad electrically connected to a solder bump;
an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad;
a voltage source electrically connected to the ohmic heating wire, and configured to increase a temperature of the ohmic heating wire above a melting temperature of the solder bump; and
a through-semiconductor via (TSV) positioned within the semiconductor region and electrically connected to the interconnect pad, wherein the semiconductor region is positioned directly between the ohmic heating wire and the TSV, the ohmic heating wire is in thermal communication with the TSV, and the ohmic heating wire has a greater electrical resistance than the TSV.

2. The IC structure of claim 1 , wherein the ohmic heating wire comprises one of a resistive metal or a resistive metal alloy.

3. The IC structure of claim 1 , wherein the interconnect pad comprises one of a plurality of interconnect pads each positioned within the semiconductor region and electrically connected to a respective solder bump, and wherein the ohmic heating wire is in thermal communication with each of the plurality of interconnect pads.

4. The IC structure of claim 1 , wherein the semiconductor region electrically insulates the ohmic heating wire from the interconnect pad.

5. The IC structure of claim 1 , wherein the interconnect pad comprises one of a plurality of interconnect pads each positioned on the semiconductor region and electrically connected to a respective through-semiconductor via (TSV), and wherein the ohmic heating wire is in thermal communication with each of the plurality of interconnect pads.

6. The IC structure of claim 1 , wherein the ohmic heating wire is electrically connected to a plurality of redundant electrical circuits each configured to transmit a current to the ohmic heating wire.

7. An integrated circuit (IC) structure, comprising:
a semiconductor region including an interconnect pad positioned on an upper surface thereof, the interconnect pad electrically connected to a solder bump;
a through-semiconductor via (TSV) extending through the semiconductor region and electrically connected to the interconnect pad;
an ohmic heating wire positioned within the semiconductor region, laterally circumventing the TSV, and in thermal communication with the TSV through the semiconductor region, wherein the semiconductor region is positioned directly between the ohmic heating wire and the TSV, the ohmic heating wire has a greater electrical resistance than the TSV, and a melting temperature of the ohmic heating wire is greater than a melting temperature of the solder bump; and
a voltage source electrically connected to the ohmic heating wire, the voltage source configured to heat the ohmic heating wire above the melting temperature of the solder bump.

8. The IC structure of claim 7 , wherein the interconnect pad comprises one of a plurality of interconnect pads each positioned within the semiconductor region and electrically connected to one of a plurality of TSVs, and wherein the ohmic heating wire is in thermal communication with each of the plurality of TSVs through the semiconductor region.

9. The IC structure of claim 7 , wherein the semiconductor region electrically insulates the ohmic heating wire from the interconnect pad.

10. The IC structure of claim 7 , wherein the ohmic heating wire is electrically connected to a plurality of redundant electrical circuits each configured to transmit a current to the ohmic heating wire.

Assignees

• Globalfoundries Inc

Inventors

• Richard Glen E
• Ayotte Stephen P
• Ding Hanyi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title