Dicing method

Patent metadata

Field	Value
Publication number	US-10256147-B2
Application number	US-201515118836-A
Country	US
Kind code	B2
Filing date	Feb 9, 2015
Priority date	Feb 14, 2014
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

The dicing method comprises the steps of providing a substrate ( 1 ) of semiconductor material, the substrate having a main surface ( 10 ), where integrated components ( 3 ) of chips ( 13 ) are arranged, and a rear surface ( 11 ) opposite the main surface, fastening a first handling wafer above the main surface, thinning the substrate at the rear surface, and forming trenches ( 20 ) penetrating the substrate and separating the chips by a single etching step after the substrate has been thinned.

First claim

The invention claimed is:

1. A dicing method, comprising:
providing a substrate of semiconductor material, the substrate having a main surface where integrated components of chips are arranged, and a rear surface opposite the main surface;
fastening a first handling wafer above the main surface;
thinning the substrate at the rear surface;
arranging a first dielectric layer on or above the rear surface;
forming openings in the first dielectric layer;
forming trenches penetrating the substrate by a single etching step after the substrate is thinned, the trenches being etched from the main surface to the openings in the first dielectric layer to separate the chips into distinct portions, wherein the single etching step is performed by dry etching;
arranging a second dielectric layer on or above the main surface;
arranging metal layers in the second dielectric layer, the metal layers being connected to the integrated components;
forming through-substrate vias from the rear surface, the through-substrate vias comprising metallizations connecting the metal layers with rear metal layers on or above the rear surface; and
applying bumps to the rear metal layers, before the trenches are etched.

2. The dicing method of claim 1 , wherein the trenches are etched from the main surface to the rear surface.

3. The dicing method of claim 1 , further comprising:
fastening a second handling wafer above the rear surface by a connecting layer; and
embedding the bumps in the connecting layer, before the trenches are etched.

4. The dicing method of claim 3 , wherein the connecting layer is formed by an adhesive.

5. The dicing method of claim 1 , wherein the trenches are etched from the rear surface to the main surface.

Assignees

• Ams Ag

Inventors

• Schrems Martin
• Stering Bernhard
• Schrank Franz

Classifications

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title