Microcontroller with variable length move instructions using direct immediate addressing or indirect register offset addressing

Patent metadata

Field	Value
Publication number	US-10255073-B2
Application number	US-201715592551-A
Country	US
Kind code	B2
Filing date	May 11, 2017
Priority date	May 12, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.

First claim

The invention claimed is:

1. An 8-bit microprocessor comprising
a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size wherein an instruction word has a payload size for an address of up to 12 bits;
a central processing unit coupled with the program memory and the data memory;
a bank select register configured to select one of up to 64 memory banks; and
an indirect addressing register operable to address up to 16 KB of data memory;
wherein the CPU is configured to execute a first move instruction comprising two instruction words and configured to only access the lower 4 KB of the data memory and a second move instruction comprising three instruction words and configured to access the entire data memory.

2. The 8-bit microprocessor according to claim 1 , wherein the bank select register comprises 6 bits.

3. The 8-bit microprocessor according to claim 1 , wherein each indirect address register comprises 14 bits.

4. The 8-bit microprocessor according to claim 1 , wherein each instruction word comprises an op-code portion.

5. The 8-bit microprocessor according to claim 4 , wherein a first instruction word of the first move instruction comprises a 12 bit source address and a second instruction word of the first move instruction comprises a 12 bit destination address thereby limiting access to the lower 4k of the data memory.

6. The 8-bit microprocessor according to claim 4 , wherein a first instruction word of the second move instruction comprises 4 bits of a source address and a second instruction word of the second move instruction comprises 10 bits of the source address and 2bits of the destination address and a third instruction word of the second move instruction comprises 12 bits of the destination address.

7. The 8-bit microprocessor according to claim 4 , wherein the CPU is further configured to execute a third move instruction comprising two instruction words, wherein a first instruction word of the third move instruction comprises a 7-bit literal offset to a 14-bit indirect address stored in an indirect address register and a second instruction word of the third move instruction comprises a 12-bit destination address which is configured to access only the lower 4K of the data memory.

8. The 8-bit microprocessor according to claim 4 , wherein the CPU is further configured to execute a fourth move instruction comprising three instruction words, wherein the first instruction word comprises only op-code, wherein a second instruction word of the fourth move instruction comprises a 7-bit literal offset to a 14-bit indirect address stored in an indirect address register and 2 bits of the destination address and the third instruction word comprises remaining 12-bit of the destination address.

9. The 8-bit microprocessor according to claim 1 , wherein a bit in an instruction word determines whether a memory bank as defined in the bank select register is accessed or whether a virtual memory bank combining data memory space of two memory banks is selected.

10. The 8-bit microprocessor according to claim 1 , further comprising a hardware multiplier and associated hardware multiplier registers and at least one set of shadow registers configured to automatically save a context when an exception occurs, wherein the context is formed by a working register, the bank select register, a status register, indirect address registers, the hardware multiplier registers and a program latch register.

11. The 8-bit microprocessor according to claim 10 , wherein a reduced context is automatically saved in a second set of shadow registers encompassing less registers than said first set of context register when a call instruction is executed, wherein the reduced context is formed by a working register, the bank select register, and a status register.

12. A method for operating an 8-bit microprocessor, comprising:
providing a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size, wherein an instruction word has a payload size for an address of up to 12 bits;
providing a central processing unit coupled with the program memory and the data memory;
providing a bank select register configured to select one of up to 64 memory banks;
providing an indirect addressing register operable to address up to 16 KB of data memory;
executing a first move instruction comprising two instruction words and configured to only access the lower 4 KB of the data memory; and
executing a second move instruction comprising three instruction words and configured to access the entire data memory.

13. The method according to claim 12 , wherein the bank select register comprises 6 bits.

14. The method according to claim 12 , wherein each indirect address register comprises 14 bits.

15. The method according to claim 12 , wherein each instruction word comprises an op-code portion.

16. The method according to claim 15 , wherein a first instruction word of the first move instruction comprises a 12 bit source address and a second instruction word of the first move instruction comprises a 12 bit destination address thereby limiting access to the lower 4k of the data memory.

17. The method according to claim 15 , wherein a first instruction word of the second move instruction comprises 4 bits of a source address and a second instruction word of the second move instruction comprises 10 bits of the source address and 2 bits of the destination address and a third instruction word of the second move instruction comprises 12 bits of the destination address.

18. The method according to claim 15 , further comprising
executing a third move instruction comprising two instruction words, wherein a first instruction word of the third move instruction comprises a 7-bit literal offset to a 14-bit indirect address stored in an indirect address register and a second instruction word of the third move instruction comprises a 12-bit destination address which is configured to access only the lower 4K of the data memory.

19. The method according to claim 15 , further comprising
executing a fourth move instruction comprising three instruction words, wherein the first instruction word comprises only op-code, wherein a second instruction word of the fourth move instruction comprises a 7-bit literal offset to a 14-bit indirect address stored in an indirect address register and 2 bits of the destination address and the third instruction word comprises remaining 12-bit of the destination address.

20. The method according to claim 13 , wherein a bit in an instruction word determines whether a memory bank as defined in the bank select register is accessed or whether a virtual memory bank combining data memory space of two memory banks is selected.

21. The method according to claim 12 , further comprising providing a hardware multiplier and associated hardware multiplier registers and at least one set of shadow registers, the method further comprises: when an exception occurs automatically saving a context, wherein the context is formed by a working register, the bank select register, a status register, indirect address registers, the hardware multiplier registers and a program latch register.

22. The method according to claim 21 , wherein a reduced context is automatically saved in a second set of shadow registers encompassing less registers than said first set of context register when a call instruction is executed, wherein the reduced context is formed by a working register, t

Assignees

• Microchip Tech Inc

Inventors

• Senapati Ashish
• Steedman Sean
• Loertscher Brent

Classifications

• G06F9/30149 Primary

  of variable length instructions · CPC title

• G06F9/342 Primary

  Extension of operand address space · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/30178

  of compressed or encrypted instructions · CPC title

• G06F9/30167

  of immediate specifier, e.g. constants · CPC title