Unified multiply unit

Patent metadata

Field	Value
Publication number	US-10255041-B2
Application number	US-201715621388-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Dec 29, 2014
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

Embodiments disclosed pertain to apparatuses, systems, and methods for performing multi-precision single instruction multiple data (SIMD) operations on integer, fixed point and floating point operands. Disclosed embodiments pertain to a circuit that is capable of performing concurrent multiply, fused multiply-add, rounding, saturation, and dot products on the above operand types. In addition, the circuit may facilitate 64-bit multiplication when Newton-Raphson, divide and square root operations are performed.

First claim

What is claimed is:

1. A processor comprising a multiplication unit, the multiplication unit comprising:
a modified booth encoder configured to:
receive one or more multipliers and one or more multiplicands;
for each of the one or more multiplicands, partition the bits in the multiplicand into overlapping groups of bits; and
generate a plurality of partial products by determining a plurality of partial product rows, wherein each of the partial product rows corresponds to a partial product as a multiplication of one of the one or more multipliers with one of the groups of bits;

a carry save adder comprising a plurality of first-level 5:3 compressors and a plurality of second-level 3:2 compressors, the carry save adder being configured to:
receive the plurality of partial products generated by the modified booth encoder; and
use the received partial products to obtain a first partial result and a second partial result; and

an adder configured to:
receive the first partial result and the second partial result;
use the received first and second partial results to determine one or more output values; and
output the one or more output values.

2. The processor of claim 1 wherein each of the first-level 5:3 compressors is configured to:
receive five input bits from five respective partial product rows, wherein a first input bit, a second input bit and a third input bit are from a first column of bits representing a one's bit position in three partial product rows, and wherein a fourth input bit and a fifth input bit are from a second column of bits representing a two's bit input position in two further partial product rows; and
output three output bits including a first output bit at the one's bit position, a second output bit at the two's bit position and a third output bit at the four's bit position.

3. The processor of claim 2 wherein each of the first-level 5:3 compressors comprises:
a first XOR gate arranged to receive the fourth and fifth input bits;
a second XOR gate arranged to receive the first and second input bits;
a third XOR gate arranged to receive the third input bit and an output from the second XOR gate;
a majority determining unit configured to receive the first, second and third input bits and to provide a bit matching the majority value of the first, second and third input bits;
a fourth XOR gate arranged to receive an output from the first XOR gate and the bit provided by the majority determining unit; and
a multiplexer arranged to receive the fourth input bit at a first data input and to receive the bit provided by the majority determining unit at a second data input, wherein the multiplexer is controlled in dependence on the output of the first XOR gate,
wherein the first output bit is the output from the third XOR gate, the second output bit is the output from the fourth XOR gate, and the third output bit is the output from the multiplexer.

4. The processor of claim 2 wherein each of the second-level 3:2 compressors is configured to:
receive three input bits from three respective first-level 5:3 compressors, wherein a first input bit is the first output bit from a first first-level 5:3 compressor, a second input bit is the second output bit from a second first-level 5:3 compressor, and a third input bit is the third output bit from a third first-level 5:3 compressor; and
output two output bits including a sum output bit and a carry output bit,
wherein the carry save adder is configured to obtain the first partial result and the second partial result based on the outputted sum output bits and the outputted carry output bits.

5. The processor of claim 4 wherein each of the second-level 3:2 compressors comprises:
a first XOR gate arranged to receive the first and second input bits;
a second XOR gate arranged to receive the third input bit and an output from the first XOR gate; and
a multiplexer arranged to receive the second input bit at a first data input and to receive the third input bit at a second data input, wherein the multiplexer is controlled in dependence on the output of the first XOR gate,
wherein the sum output bit is the output from the second XOR gate, and the carry output bit is the output from the multiplexer.

6. The processor of claim 1 wherein the carry save adder comprises one or more further levels of 4:2 compressors.

7. The processor of claim 1 wherein each partial product row is offset from an immediately preceding partial product row by two bits.

8. The processor of claim 1 wherein each overlapping group of bits comprises three bits.

9. The processor of claim 1 wherein each of the multipliers comprises 8 bits, and each of the multiplicands comprises 8 bits.

10. The processor of claim 9 wherein there are five overlapping groups of bits per multiplicand.

11. The processor of claim 1 wherein said one or more multipliers comprises eight multipliers and said one or more multiplicands comprises eight multiplicands.

12. The processor of claim 1 wherein each of the multipliers comprises 16 bits, and each of the multiplicands comprises 16 bits.

13. The processor of claim 12 wherein there are nine overlapping groups of bits per multiplicand.

14. The processor of claim 1 wherein each of the one or more output values is the product of one of the one or more multiplier operands and one of the one or more multiplicand operands.

15. The processor of claim 1 wherein the first partial result comprises a sequence of partial sum bits and the second partial result comprises a sequence of carry bits.

16. The processor of claim 1 wherein the adder is configured to include one or more additional columns of bits between at least some of the output values, wherein each of the additional columns is either:
a break column which prevents propagation of carries across the additional column, or
a propagate column which allows propagation of carries across the additional column.

17. A non-transitory computer-readable medium comprising executable instructions to describe a processor comprising a multiplication unit, the multiplication unit comprising:
a modified booth encoder configured to:
receive one or more multipliers and one or more multiplicands;
for each of the one or more multiplicands, partition the bits in the multiplicand into overlapping groups of bits; and
generate a plurality of partial products by determining a plurality of partial product rows, wherein each of the partial product rows corresponds to a partial product as a multiplication of one of the one or more multipliers with one of the groups of bits;

a carry save adder comprising a plurality of first-level 5:3 compressors and a plurality of second-level 3:2 compressors, the carry save adder being configured to:
receive the plurality of partial products generated by the modified booth encoder; and
use the received partial products to obtain a first partial result and a second partial result; and

an adder configured to:
receive the first partial result and the second partial result;
use the received first and second partial results to determine one or more output values; and
output the one or more output values.

18. The computer-readable medium of claim 17 wherein each of the first-level 5:3 compressors is configured to receive five input bits from five respective partial product rows, wherein a first input bit, a second input bit and a third input bit are from a first column of bits representing a one's bit position in three partial product rows, and wherein a fourth input bit and a fifth input bit are f

Assignees

• Imagination Tech Ltd

Inventors

• Rarick Leonard

Classifications

• G06F7/487 Primary

  Multiplying; Dividing {(G06F7/4833, G06F7/4836 take precedence)} · CPC title