Data transmission between asychronous environments

Patent metadata

Field	Value
Publication number	US-10250419-B2
Application number	US-201715651364-A
Country	US
Kind code	B2
Filing date	Jul 17, 2017
Priority date	Oct 1, 2012
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.

First claim

What is claimed is:

1. A method of providing signals across a first electrical domain and a second electrical domain, the method comprising:
outputting a data element from a first electronic element to a second electronic element via at least two duplicate electrical paths, the first and the second electrical domains differing by at least one of: voltage and clock frequency, wherein the first electrical domain transmits data of the data element to the second electrical domain over a selected electrical path of the at least two duplicate electrical paths, the selected electrical path being selected from the at least two duplicate electrical paths in round robin fashion, wherein the data of the data element arrives at the second electronic element in a same order that the data of the data element is outputted from the first electronic element; and
changing the selected electrical path in the round robin fashion with each clock cycle.

2. The method of claim 1 , wherein the first and the second electrical domains differ by clock frequency such that the first electrical domain uses a first clock frequency and the second electrical domain uses a second clock frequency, both the first and the second clock frequencies being at least 1 GHz.

3. The method of claim 1 , wherein all of the at least two duplicate electrical paths provide for the data of the data element to be transmitted to the second electronic element.

4. The method of claim 1 , wherein selecting the electrical path in round robin fashion includes supplying the data of the data element to a first switch that alternates sending the data of the data element to each of at least two duplicate electrical paths.

5. The method of claim 1 , wherein each of the at least two duplicate electrical paths contains identical electrical elements such that each electrical element in a first one of the at least two duplicate electrical paths has an analogous element in a second one of the at least two duplicate electrical paths and each electrical element in the second one of the at least two duplicate electrical paths has an analogous element in the first one of the at least two duplicate electrical paths, creating a one-to-one correspondence of elements between the first and the second ones of the at least two duplicate electrical paths.

6. The method of claim 1 , further including obtaining a value indicative of at least one of: the voltage and the clock frequency of the second electrical domain.

7. The method of claim 6 , further including multiplexing the value indicative of at least one of: the voltage and the clock frequency of the second electrical domain with the data of the data element.

8. The method of claim 7 , further including passing a result of the multiplexing through a level shifter.

9. The method of claim 8 , wherein receiving the data element at the second electronic element includes receiving the data of the data element from a second switch that alternates sending the data of the data element from each of the at least two duplicate electrical paths.

10. The method of claim 8 , wherein the level shifter obtains the value indicative of at least one of: the voltage and the clock frequency of the second electrical domain from the multiplexed result.

11. The method of claim 10 , wherein the level shifter uses the value indicative of at least one of: the voltage and the clock frequency to convert the data element into the voltage and/or clock frequency from the second electrical domain.

12. The method of claim 1 , wherein the at least two duplicate electrical paths include only two paths.

13. An electrical circuit operable to transmit data across electrical domains, the circuit including:
a first electronic element in a first electrical domain, elements within the first electrical domain operating according to a first operational voltage and a first clock frequency;
a first switch in the first electrical domain, operating according to the first operational voltage and the first clock frequency, the first switch having an input electrically coupled to an output of the first electronic element, the first switch having at least two outputs, the first switch sending data on each of the at least two outputs in round robin fashion;
a second electronic element in a second electrical domain, elements within the second electrical domain operating according to a second operational voltage and a second clock frequency, each of the at least two outputs of the first switch being coupled to a respective one of duplicate electrical paths leading to the second electronic element, the first and the second electrical domains differing by a parameter selected from the group consisting of voltage and clock frequency; and
a second switch in the second electrical domain, the second switch having at least two inputs electrically coupled to respective ones of the at least two outputs of the first switch via the respective one of the duplicate electrical paths, the second switch having an output electrically coupled to an input of the second electronic element, wherein the data arrives at the second electronic element in a same order that the data is outputted from the first electronic element and wherein the respective one of the duplicate electrical paths that the data arrives in is changed in the round robin fashion during each clock cycle.

14. A non-transitory computer readable medium containing instructions thereon, that when executed by at least one processor cause the at least one processor to:
apply a clock signal to a first electronic element in a first electrical domain, all elements in the first electrical domain operating responsive to the clock signal;
output a data element from the first electronic element including supplying the data element to a switch that alternates sending the data element to each of at least two duplicate electrical paths in round robin fashion;
change each of the at least two duplicate electrical paths in the round robin fashion with each clock cycle; and
receive the data element at a second electronic element in a second electrical domain, the first and the second electrical domains differing by a parameter selected from the group consisting of voltage and clock frequency, wherein the data element is received at the second electronic element in a same order that the data element is outputted from the first electronic element.

15. The computer readable medium of claim 14 , wherein the instructions are embodied in hardware description language suitable for one or more of describing, designing, organizing, fabricating, or verifying hardware.

16. The computer readable medium of claim 14 , wherein the first and the second electrical domains differ by clock frequency such that the first electrical domain uses a first clock frequency and the second electrical domain uses a second clock frequency, both the first and the second clock frequencies being at least 1 GHz.

Assignees

• Ati Technologies Ulc
• Advanced Micro Devices Inc

Inventors

• Sung Andy
• Lai Leon
• Wang Daniel

Classifications

• H04L27/00 Primary

  Modulated-carrier systems · CPC title

• G06F5/06 Primary

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• H04L7/005

  Correction by an elastic buffer · CPC title