Vertical memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10249636-B2
Application number	US-201715692606-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Nov 10, 2015
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

First claim

What is claimed is:

1. A method of manufacturing a vertical memory device, the method comprising:
forming a support layer on a substrate;
alternately forming sacrificial layers and insulation layers on the support layer in a first direction perpendicular to an upper surface of the substrate;
forming a channel hole and a dummy channel hole through the support layer, the sacrificial layers and the insulation layers,
the dummy channel hole exposing the upper surface of the substrate;

removing a part of the support layer exposed by the channel hole and the dummy channel hole to enlarge lower portions of the channel hole and the dummy channel holes so that the channel hole and the dummy channel hole are in communication with each other, a remaining portion of the support layer forming a support pattern;
forming a channel filling the channel hole;
forming a dummy channel filling the dummy channel hole;
forming an opening through the support pattern, the insulation layers and the sacrificial layers to expose the upper surface of the substrate, the forming the opening through the support pattern including transforming the insulation layers and the sacrificial layers into insulation patterns and sacrificial patterns, respectively;
removing the sacrificial patterns to form a plurality of first gaps; and
forming gate electrodes to fill the first gaps, respectively.

2. The method of claim 1 , further comprising:
partially removing the support pattern exposed by the opening to form a second gap exposing the upper surface of the substrate and an outer sidewall of the channel; and
performing an SEG process to form an epitaxial layer on the upper surface of the substrate exposed by the opening and the second gap, wherein
the epitaxial layer contacts the outer sidewall of the channel, and
the partially removing the support pattern exposed by the opening and the performing the SEG process are performed prior to removing the sacrificial patterns to form the plurality of first gaps.

3. The method of claim 2 , wherein partially removing the support pattern exposed by the opening includes a wet etching process.

4. The method of claim 2 , wherein
the forming the channel hole and the dummy channel hole includes forming a plurality of channel holes both in second and third directions and forming a plurality of dummy channel holes disposed in the second direction between the channel holes,
the second and third directions are parallel to the upper surface of the substrate and perpendicular to each other,
and, after forming the second gap, the support pattern remains between the channel holes or between the channel holes and the dummy channel holes.

5. The method of claim 4 , wherein
the opening extends in the second direction,
and the partially removing the support pattern exposed by the opening includes removing a portion of the support pattern that is adjacent to the opening and extends in the second direction.

6. The method of claim 2 , wherein
the epitaxial layer fills the second gap, and
a top surface of the epitaxial layer contacts a lower surface of a lowermost one of the sacrificial layers.

7. The method of claim 2 , wherein
the epitaxial layer partially fills the second gap, and
a top surface of the epitaxial layer does not contact a lower surface of a lowermost one of the sacrificial layers.

8. The method of claim 2 , further comprising:
forming an oxide layer by oxidizing an upper portion of the epitaxial layer.

9. The method of claim 2 , further comprising:
forming an etch stop layer on the support layer prior to the alternately forming the sacrificial layers and the insulation layers,
wherein the partially removing the support pattern exposed by the opening to form the second gap includes limiting a lowermost one of the sacrificial layers from being etched with the etch stop layer.

10. The method of claim 1 , wherein the support layer includes a material having an etching selectivity with respect to the sacrificial layers and the insulation layers.

11. A method of manufacturing a vertical memory device, the method comprising:
forming a support layer on a substrate;
alternately forming sacrificial layers and insulation layers on the support layer in a first direction perpendicular to an upper surface of the substrate;
forming a channel hole through the support layer, the sacrificial layers, and the insulation layers;
forming a channel to fill the channel hole;
forming an opening through the support layer, the sacrificial layers and the insulation layers to expose the upper surface of the substrate, the forming the opening including transforming the insulation layers and the sacrificial layers into insulation patterns and sacrificial patterns, respectively;
removing a part of the support layer exposed by the opening to form a first gap exposing the upper surface of the substrate and an outer sidewall of the channel;
forming a silicon-containing layer on the upper surface of the substrate exposed by the opening and the first gap, the silicon-containing layer contacting the outer sidewall of the channel;
removing the sacrificial patterns to form a plurality of second gaps; and
forming gate electrodes to fill the second gaps, respectively.

12. The method of claim 11 , wherein
the forming the channel hole includes forming a channel array including a plurality of channel hole columns in a third direction parallel to the upper surface of the substrate,
each of the channel hole columns including a plurality of channel holes disposed in a second direction parallel to the upper surface of the substrate and perpendicular to the third direction, and
the forming the channel includes forming a plurality of channels filling the plurality of channel holes, respectively.

13. The method of claim 12 , further comprising:
partially removing the support layer exposed by the channel holes to enlarge a lower portion of each of the channels, wherein
the partially removing the support layer is performed prior to forming the channels filling the channel holes, respectively.

14. The method of claim 13 , wherein the channel holes are not in communication with each other even if the lower portions of the channel holes are enlarged.

15. The method of claim 13 , wherein
the opening extends in the second direction,
and the partially removing the support layer exposed by the opening includes forming a support pattern extending in the second direction.

16. A method of manufacturing a vertical memory device, the method comprising:
forming a support layer on a substrate;
alternately forming sacrificial layers and insulation layers on the support layer in a first direction perpendicular to an upper surface of the substrate;
forming a channel hole and a dummy channel hole through the support layer, the sacrificial layers and the insulation layers;
removing a part of the support layer exposed by the channel hole and the dummy channel hole to enlarge lower portions of the channel hole and the dummy channel holes, a remaining portion of the support layer forming a support pattern;
forming a channel and a dummy channel filling the channel hole and the dummy channel hole, respectively, the channel and the dummy channel contacting each other;
forming an opening through the support pattern, the insulation layers and the sacrificial layers to expose the upper surface of the substrate, the forming the opening including transforming the insulation layers and the sacrificial layers into insulation patterns and sacrificial patterns, respectively;
replacing the sacrificial patterns wi

Assignees

• Yun Jang Gn
• Xia Zhiliang
• Moon Ahn Sik
• Park Se Jun
• Lim Joon Sung
• Hwang Sung Min
• Samsung Electronics Co Ltd

Inventors

• Yun Jang-Gn
• Xia Zhiliang
• Moon Ahn-Sik
• Park Se-Jun
• Lim Joon-Sung
• Hwang Sung-Min

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic