Semiconductor device having buried gate structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10249628-B2
Application number	US-201815865467-A
Country	US
Kind code	B2
Filing date	Jan 9, 2018
Priority date	May 21, 2014
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a device isolation region defining an active region in a substrate; and
gate structures buried in the active region of the substrate,
wherein at least one of the gate structures comprises:
a gate trench;
a gate insulating layer formed on the entire inner wall of the gate trench;
a gate barrier pattern formed on the gate insulating layer disposed on a lower portion of the gate trench;
a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench; and
a gate capping insulating layer formed on the gate electrode pattern and the gate barrier pattern to fill the upper portion of the gate trench,
wherein the gate barrier pattern has a top surface which is lower than a top of the gate electrode pattern,
wherein the top surface of the gate barrier pattern is in contact with an insulating layer.

2. The semiconductor device of claim 1 , further comprising a buffer oxide layer formed on the gate electrode pattern.

3. The semiconductor device of claim 2 , wherein the gate insulating layer covers outside wall of the gate barrier pattern and side wall of the buffer oxide layer.

4. The semiconductor device of claim 2 , further comprising an electrode protection layer,
wherein at least portion of the electrode protection layer is interposed between the buffer oxide layer and the gate electrode pattern on the upper end of the recessed gate barrier pattern.

5. The semiconductor device of claim 4 , wherein a portion of the electrode protection layer is interposed between the gate insulating layer and the gate electrode pattern.

6. The semiconductor device of claim 4 , wherein the top of the gate barrier pattern is in contact with the electrode protection layer.

7. The semiconductor device of claim 2 , wherein the buffer oxide layer includes silicon oxide containing N-type impurities.

8. The semiconductor device of claim 7 , further comprising a source area disposed between the gate structures,
wherein the source area includes the same dopant as the N-type impurities included in the buffer oxide layer.

9. The semiconductor device of claim 8 , further comprising a bit-line contact plug vertically aligned with and overlapping the source area,
wherein a side of a bottom surface and a bottom of a side surface of the bit-line contact plug contacts the gate capping insulating layer or the buffer oxide layer.

10. The semiconductor device of claim 2 , wherein a bottom and side surfaces of the gate capping insulating layer are covered by the buffer oxide layer.

11. The semiconductor device of claim 2 , wherein the top surface of the gate barrier pattern is in contact with the buffer oxide layer.

12. A semiconductor device, comprising:
gate structures buried in a substrate;
a bit-line contact plug formed on the substrate to be vertically aligned with the substrate between the gate structures;
a bit-line structure formed on the bit-line contact plug; and
a spacer layer covering the bit-line structure,
wherein each of the gate structures includes:
a gate trench formed in the substrate;
a gate insulating layer formed on the entire inner wall of the gate trench;
a gate barrier pattern formed on the gate insulating layer disposed on a lower portion of the gate trench;
a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench; and
a silicon nitride layer formed on the gate electrode pattern and the gate barrier pattern to fill the upper portion of the gate trench,
wherein the gate barrier pattern has a top surface which is lower than a top of the gate electrode pattern,
wherein the top surface of the gate barrier pattern is in contact with an insulating layer.

13. The semiconductor device of claim 12 , further comprising a buffer oxide layer formed on the gate electrode pattern.

14. The semiconductor device of claim 13 , wherein the top surface of the gate barrier pattern is in contact with the buffer oxide layer.

15. The semiconductor device of claim 3 further comprising an electrode protection layer conformally formed on around a lower portion of the buffer oxide layer,
wherein the top of the gate barrier pattern is in contact with the electrode protection layer.

16. A semiconductor device, comprising:
a device isolation region defining an active region in a substrate;
gate structures buried in the active region of the substrate;
a bit-line contact plug formed on the substrate to be vertically aligned with the active region between the gate structures; and
a bit-line structure formed on the bit-line contact plug,
wherein each of the gate structures comprises:
a gate trench formed in the substrate;
a gate insulating layer formed on the entire inner wall of the gate trench;
a gate barrier pattern formed on the gate insulating layer disposed on a lower portion of the gate trench;
a gate electrode pattern formed on the gate harrier pattern and filling the lower portion of the gate trench; and
a gate capping insulating layer formed on the gate electrode pattern and the gate barrier pattern to fill the upper portion of the gate trench,
wherein an upper end of the gate barrier pattern is recessed to be lower than an upper end of the gate electrode pattern,
wherein the top surface of the gate barrier pattern is in contact with an insulating layer.

17. The semiconductor device of claim 16 , wherein a lower portion of the bit-line contact plug protrudes downward to be lower than an upper surface of the substrate to be in contact with the gate capping insulating layer.

18. The semiconductor device of claim 16 , wherein the active region comprises:
a source area disposed between the gate structures; and
drain areas disposed between the device isolation region and the gate structures,
wherein the source area, and the drain areas include N-type dopants.

19. The semiconductor device of claim 16 , further comprising an electrode protection layer disposed on the electrode pattern,
wherein the upper end of the gate barrier pattern is in contact with the electrode protection layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Min-Hee

Classifications

• H01L27/10885

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic

• H01L27/10823 Primary

  Electricity · mapped topic