Semiconductor device having buried gate structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9437697-B2
Application number	US-201414551857-A
Country	US
Kind code	B2
Filing date	Nov 24, 2014
Priority date	May 21, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a device isolation region defining an active region in a substrate; and
gate structures buried in the active region of the substrate,
wherein at least one of the gate structures comprises:
a gate trench;
a gate insulating layer formed on an inner wall of the gate trench;
a gate barrier pattern formed on the gate insulating layer disposed on a lower portion of the gate trench;
a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench;
an electrode protection layer formed on the gate insulating layer disposed on an upper portion of the gate trench and contacting the gate electrode pattern, wherein a bottom surface of the electrode protection layer is in contact with an upper surface of the gate barrier pattern and wherein a portion of the electrode protection layer is disposed between the gate insulating layer and the gate electrode pattern;
a buffer oxide layer formed on the electrode protection layer; and
a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench,
wherein the buffer oxide layer is U-shaped, and wherein a bottom and side surfaces of the gate capping insulating layer are covered by the buffer oxide layer.

2. The semiconductor device of claim 1 , wherein the gate insulating layer is formed on the entire inner wall of the gate trench.

3. The semiconductor device of claim 1 , wherein the electrode protection layer includes silicon nitride.

4. The semiconductor device of claim 1 , wherein the buffer oxide layer includes silicon oxide containing N-type impurities.

5. The semiconductor device of claim 4 , further comprising a source area disposed between the gate structures,
wherein the source area includes the same dopant as the N-type impurities included in the buffer oxide layer.

6. The semiconductor device of claim 5 , further comprising a bit-line contact plug vertically aligned with and overlapping the source area,
wherein a side of a bottom surface and a bottom of a side surface of the bit-line contact plug contacts the gate capping insulating layer, the buffer oxide layer, and the electrode protection layer.

7. The semiconductor device of claim 6 , wherein a horizontal width of the bit-line contact plug is greater than a horizontal width of the source area.

8. The semiconductor device of claim 6 , further comprising a bit-line structure disposed on the bit-line contact plug,
wherein an upper surface of the bit-line contact plug exposed without being vertically overlapped by the bit-line structure is slanted.

9. The semiconductor device of claim 8 , further comprising a silicon oxide layer formed on the slanted upper surface of the bit-line contact plug.

10. The semiconductor device of claim 8 , further comprising a lower interlayer insulating layer,
wherein the slanted upper surface of the bit line contact plug is recessed to be lower than an upper surface of the lower interlayer insulating layer.

11. The semiconductor device of claim 10 , further comprising a spacer layer covering the bit-line structure,
wherein the spacer layer is formed on the slanted upper surface of the recessed bit-line contact plug.

12. The semiconductor device of claim 1 , wherein the gate capping insulating layer includes silicon nitride.

13. The semiconductor device of claim 1 , wherein an upper end of the gate barrier pattern is recessed to be lower than an upper end of the gate electrode pattern.

14. The semiconductor device of claim 13 , wherein a portion of the electrode protection layer is interposed between the gate insulating layer and the gate electrode pattern on the upper end of the recessed gate barrier pattern.

15. A semiconductor device, comprising:
gate structures buried in a substrate;
a bit-line contact plug formed on the substrate to be vertically aligned with the substrate between the gate structures;
a bit-line structure formed on the bit-line contact plug; and
a spacer layer covering the bit-line structure,
wherein each of the gate structures includes:
a gate trench formed in the substrate;
a gate insulating layer formed on an inner wall of the gate trench;
a gate barrier pattern formed on the gate insulating layer disposed on a lower portion of the gate trench;
a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench;
a silicon oxide layer formed on the gate insulating layer disposed on an upper portion of the gate trench;
a silicon nitride layer formed on the silicon oxide layer to fill the upper portion of the gate trench,
wherein the silicon oxide layer is U-shaped, and wherein a bottom and side surfaces of the silicon nitride layer are covered by the silicon oxide layer; and
an electrode protection layer conformally formed around a lower portion of the silicon oxide layer, wherein a bottom surface of the electrode protection layer is in contact with an upper surface of the gate barrier pattern, and wherein a portion of the electrode protection layer is disposed between the gate insulating layer and the gate electrode pattern.

16. The semiconductor device of claim 15 , further comprising a silicon nitride layer conformally formed between the gate insulating layer and the silicon oxide layer.

17. The semiconductor device of claim 15 , wherein an upper end of the gate barrier pattern is recessed to be lower than an upper end of the gate electrode pattern, resulting in forming a gap between the gate insulating layer and the gate electrode pattern, and
a portion of the silicon oxide layer fills the gap.

18. The semiconductor device of claim 15 , wherein the silicon oxide layer includes phosphorus (P).

19. A semiconductor device, comprising:
a device isolation region defining an active region in a substrate;
gate structures buried in the active region of the substrate;
a bit-line contact plug formed on the substrate to be vertically aligned with the active region between the gate structures; and
a bit-line structure formed on the bit-line contact plug,
wherein each of the gate structures comprises:
a gate trench formed in the substrate;
a gate insulating layer formed on an inner wall of the gate trench;
a gate barrier pattern formed on the gate insulating layer disposed on a lower portion of the gate trench;
a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench;
a silicon nitride layer formed on the gate insulating layer disposed on an upper portion of the gate trench and contacting the gate barrier pattern and the gate electrode pattern;
a silicon oxide layer formed on the gate insulating layer disposed on the upper portion of the gate trench; and
a gate capping insulating layer formed on the silicon oxide layer to fill the upper portion of the gate trench,
wherein an upper end of the gate barrier pattern is recessed to be lower than an upper end of the gate electrode pattern, and
a lower portion of the bit-line contact plug protrudes downward to be lower than an upper surface of the substrate to be in contact with the silicon nitride layer, the silicon oxide layer, and the gate capping insulating layer.

20. The semiconductor device of claim 19 , wherein the active region comprises:
a source area disposed between the gate structures; and
drain areas disposed between the device isolation region and the gate structures,
wherein the silicon oxide layer, the source area, an

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Min-Hee

Classifications

• H10D30/667

  having substrates comprising insulating layers, e.g. SOI-VDMOS transistors · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/27

  Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates · CPC title