Apparatuses for communication systems transceiver interfaces

Patent metadata

Field	Value
Publication number	US-10249609-B2
Application number	US-201715674218-A
Country	US
Kind code	B2
Filing date	Aug 10, 2017
Priority date	Aug 10, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a first bipolar junction transistor (BJT) and a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), where a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT. The integrated circuit device additionally includes a triggering device comprising a first diode having a cathode electrically connected to the base of the first BJT. The integrated circuit device further includes a third BJT cross-coupled with the second BJT to operate as a second SCR, where the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a first bipolar junction transistor (BJT);
a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), wherein a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT;
a triggering device comprising a first triggering device configured to provide a triggering current to the base of the first BJT; and
a third BJT cross-coupled with the second BJT to operate as a second SCR, wherein the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.

2. The integrated circuit device of claim 1 , further comprising a first well of a first type configured as the base of the first BJT, wherein the first well of the first type is interposed between a first well of a second type configured as the collector of the first BJT and a second well of the second type configured as an emitter of the first BJT, wherein the first well of the first type further has formed therein a first heavily doped region of the second type.

3. The integrated circuit device of claim 2 , wherein the first triggering device is connected to the base of the first BJT through the first heavily doped region of the second type.

4. The integrated circuit device of claim 2 , further comprising a plurality of metallization levels formed above a semiconductor substrate in which the first BJT, the second BJT, the third BJT, and the triggering device are formed, wherein the first triggering device is electrically connected to the base of the first BJT through one or more of the metallization levels.

5. The integrated circuit device of claim 2 , wherein the first well of the second type is further configured as the base of the second BJT, wherein the base of the second BJT is formed between a first heavily doped region of the first type formed in the first well of the second type and configured as an emitter of the second BJT and a deep well of the first type formed under the first well of the second type and configured as the collector of the second BJT.

6. The integrated circuit device of claim 1 , further comprising a first terminal (T 1 ) and a second terminal (T 2 ), wherein the first SCR is configured as a bidirectional SCR comprising a cathode/anode (K/A) electrically connected to the T 1 and an anode/cathode (A/K) electrically connected to the T 2 , wherein the integrated circuit device is configured to activate in response to an electrical overstress signal received between the T 1 and T 2 .

7. The integrated circuit device of claim 6 , wherein the triggering device comprises a first diode having a cathode electrically connected to the base of the first BJT and a second diode having a cathode electrically connected to the base of the first BJT, and wherein an anode of the first diode is electrically connected to the T 1 and wherein an anode of the second diode is electrically connected to the T 2 .

8. The integrated circuit device of claim 7 , further comprising a fourth BJT cross-coupled with the second BJT to operate as a third SCR, wherein the fourth BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.

9. The integrated circuit device of claim 1 , wherein the first triggering device comprises at least one of a triggering diode or a triggering BJT.

10. The integrated circuit device of claim 9 , further comprising a first well of a first type configured as the base of the first BJT, wherein the first well of the first type is interposed between a first well of a second type configured as the collector of the first BJT and a second well of the second type configured as an emitter of the first BJT, wherein the first well of the second type further comprises a heavily doped region of the first type and a heavily doped region of the second type that are commonly connected to a terminal of the integrated circuit device.

11. An integrated circuit device, comprising:
a semiconductor substrate having formed therein a bidirectional semiconductor-controlled rectifier (SCR), the bidirectional SCR formed between a first terminal and a second terminal, wherein the bidirectional SCR comprises a central well of a first type having formed therein a central heavily doped region of a second type;
one or more metallization levels formed above the semiconductor substrate; and
a pair of triggering devices each electrically connected to the central well of the first type through the one or more metallization levels.

12. The integrated circuit device of claim 11 , wherein the bidirectional SCR comprises a first bipolar junction transistor (BJT) having the central well of the first type configured as a base, the bidirectional SCR further comprising a first well of the second type configured as a collector of the first BJT and a second well of the second type configured as an emitter of the first BJT, wherein the central well of the first type is interposed between the first and second wells of the second type.

13. The integrated circuit device of claim 12 , wherein the bidirectional SCR further comprises first and second electrically floating metal layers formed on the central well of the first type, wherein the first and second electrically floating layers are laterally interposed by the central heavily doped region of the second type.

14. The integrated circuit device of claim 12 , wherein the bidirectional SCR further comprises a second BJT cross-coupled with the first BJT to operate as the bidirectional SCR, wherein a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT.

15. The integrated circuit device of claim 14 , further comprising a deep well of the first type, wherein each of the central well of the first type and first and second wells of the second type is formed in the deep well of the first type.

16. The integrated circuit device of claim 15 , wherein the second BJT comprises a heavily doped region of the first type serving as an emitter formed in the first well of the second type, the first well of the second type serving as a base of the second BJT and the deep well of the first type serving as a collector of the second BJT.

17. The integrated circuit device of claim 14 , further comprising a third BJT cross-coupled with the second BJT to operate as a second SCR, wherein the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.

18. The integrated circuit device of claim 17 , wherein the central heavily doped region of the second type is configured as an emitter of the third BJT, the central well of the first type is configured as a base of the third BJT and the first well of the second type is configured as a collector of the third BJT.

19. The integrated circuit device of claim 11 , wherein each of the pair of triggering devices comprises at least one of a triggering diode or a triggering BJT.

20. The integrated circuit device of claim 19 , wherein the bidirectional SCR comprises a first bipolar junction transistor (BJT) having the central well of the first type configured as a base, the bidirectional SCR further comprising a first well of the second type configured as a collector of the first BJT and a second well of the second type configured as an emitter of the

Assignees

• Analog Devices Inc

Inventors

• Salcedo Javier Alejandro
• He Linfeng

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title