Apparatus and methods for electrostatic discharge protection of radio frequency interfaces

Patent metadata

Field	Value
Publication number	US-9831666-B2
Application number	US-201514797770-A
Country	US
Kind code	B2
Filing date	Jul 13, 2015
Priority date	May 15, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first pin and a second pin;
a substrate; and
an electrostatic discharge (ESD) protection circuit over the substrate, wherein the ESD protection circuit comprises:
a forward ESD protection circuit configured to provide protection against a positive polarity ESD event received between the first pin and the second pin, wherein the forward ESD protection circuit comprises a first diode of a first type having an anode electrically connected to the first pin; and
a reverse ESD protection circuit configured to provide protection against a negative polarity ESD event received between the first pin and the second pin, wherein the reverse ESD protection circuit comprises a first diode of a second type having a cathode electrically connected to the first pin,

wherein a capacitance between the substrate and the anode of the first diode of the first type is less than a capacitance between the substrate and a cathode of the first diode of the first type, and wherein a capacitance between the substrate and the cathode of the first diode of the second type is less than a capacitance between the substrate and an anode of the first diode of the second type.

2. The integrated circuit of claim 1 , wherein the first diode of the first type comprises a P+/N-EPI diode, and wherein the first diode of the second type comprises a P-EPI/N+ diode.

3. The integrated circuit of claim 2 , further comprising:
an insulator layer over the substrate;
an N-EPI layer over the insulator layer; and
a P+ region in the N-EPI layer, wherein the first diode of the first type comprises a p-n junction at an interface between the P+ region and the N-EPI layer.

4. The integrated circuit of claim 3 , wherein no n-type buried layer (NBL) is between the N-EPI layer and the insulator layer.

5. The integrated circuit of claim 2 , further comprising:
an insulator layer over the substrate;
a P-EPI layer over the insulator layer; and
an N+ region in the P-EPI layer, wherein the first diode of the second type comprises a p-n junction at an interface between the P-EPI layer and the N+ region.

6. The integrated circuit of claim 3 , wherein no p-type buried layer (PBL) is between the P-EPI layer and the insulator layer.

7. The integrated circuit of claim 1 , wherein the capacitance between the substrate and the anode of the first diode of the first type is less than the capacitance between the substrate and the cathode of the first diode of the first type by at least a factor of 2, and wherein the capacitance between the substrate and the cathode of the first diode of the second type is less than the capacitance between the substrate and the anode of the first diode of the second type by at least a factor of 2.

8. The integrated circuit of claim 1 , wherein the forward ESD protection circuit further comprises a first diode of the second type having a cathode electrically connected to the second pin, and wherein the reverse ESD protection circuit further comprises a first diode of the first type having an anode electrically connected to the second pin.

9. The integrated circuit of claim 8 ,
wherein the forward ESD protection circuit further comprises one or more ESD protection devices electrically connected in series in an electrical path between the cathode of the first diode of the first type and an anode of first diode of the second type,
wherein the reverse ESD protection circuit further comprises one or more ESD protection devices electrically connected in series in an electrical path between the cathode of the first diode of the first type and an anode of first diode of the second type.

10. The integrated circuit of claim 9 ,
wherein the one or more ESD protection devices of the forward ESD protection circuit comprises at least one silicon controlled rectifier (SCR) device, and wherein the one or more ESD protection devices of the reverse ESD protection circuit comprises at least one SCR device.

11. The integrated circuit of claim 1 , wherein the first pin comprises a radio frequency signal pin and the second pin comprises a radio frequency ground pin.

12. The integrated circuit of claim 11 , further comprising a radio frequency circuit electrically connected to the radio frequency signal pin.

13. The integrated circuit of claim 11 , wherein the radio frequency signal pin is configured to receive a radio frequency signal that swings above and below a voltage of the radio frequency ground pin.

14. The integrated circuit of claim 8 , further comprising a radio frequency circuit electrically connected to the radio frequency signal pin.

15. A method of electrostatic discharge (ESD) protection, the method comprising:
protecting a first pin of an integrated circuit from a positive polarity ESD event using a forward ESD protection circuit;
protecting the first pin from a negative polarity ESD event using a reverse ESD protection circuit;
isolating the first pin from a capacitance of the forward ESD protection circuit to a substrate of the integrated circuit using a first diode of a first type, wherein the first diode of the first type has an anode electrically connected to the first pin, and wherein a capacitance between the substrate and the anode of the first diode of the first type is less than a capacitance between the substrate and a cathode of the first diode of the first type; and
isolating the first pin from a capacitance of the reverse ESD protection circuit to the substrate using a first diode of a second type, wherein the first diode of the second type has a cathode electrically connected to the first pin, and wherein a capacitance between the substrate and the cathode of the first diode of the second type is less than a capacitance between the substrate and an anode of the first diode of the second type.

16. The method circuit of claim 15 , wherein isolating the first pin from the capacitance of the forward ESD protection circuit to the substrate comprises using a P+/N-EPI diode, and wherein isolating the first pin from the capacitance of the reverse ESD protection circuit to the substrate comprises using a P-EPI/N+ diode.

17. The method circuit of claim 15 , wherein protecting the first pin from a positive polarity ESD event comprises activating an electrical path from the first pin to a second pin through the forward ESD protection circuit, wherein the forward ESD protection circuit comprises a series combination of one or more diodes of the first type, one or more ESD protection devices, and one or more diodes of the second type.

18. The method circuit of claim 17 , wherein protecting the first pin from a negative polarity ESD event comprises activating an electrical path from the first pin to the second pin through the reverse ESD protection circuit, wherein the reverse ESD protection circuit comprises a series combination of one or more diodes of the first type, one or more ESD protection devices, and one or more diodes of the second type.

19. An integrated circuit comprising:
a first pin;
a second pin;
a forward ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin, wherein a first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin; and
a reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connect

Assignees

• Analog Devices Inc

Inventors

• Parthasarathy Srivatsan
• Salcedo Javier Alejandro
• Carrillo-Ramirez Rodrigo

Classifications

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H02H9/04

  responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T) · CPC title

• H01L27/0248

  Electricity · mapped topic

• H10D89/811 Primary

  using FETs as protective elements · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title