Forming TS cut for zero or negative TS extension and resulting device

Patent metadata

Field	Value
Publication number	US-10249535-B2
Application number	US-201715433188-A
Country	US
Kind code	B2
Filing date	Feb 15, 2017
Priority date	Feb 15, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.

First claim

What is claimed is:

1. A method comprising:
forming two gates across and perpendicular to first and second pairs of fins on a substrate;
forming first and second pairs of raised source/drain (RSD) between the two gates on the first and second pairs of fins, respectively;
forming a planar self-aligned contact (SAC) cap on each of the two gates;
forming a metal layer over the substrate coplanar with an upper surface of the SACs;
forming an oxide layer over the substrate subsequent to forming the metal layer;
forming a nitride layer over the oxide layer;
patterning the oxide and nitride layers, forming first and second oxide and nitride stacks above the first and second pairs of RSD, respectively, the first and second oxide and nitride stacks formed perpendicular to the two gates and each having with a width equal to or less than an overall width of a pair of fins;
etching the metal layer proximate to the oxide and nitride stacks forming trench silicide (TS) structure upper portions above the first and second pairs of RSD, and forming the TS structure in the metal layer over and perpendicular to the fins, the TS structure having first and second upper portions over the first and second pairs of RSD, respectively, each upper portion having a width equal to or less than an overall width of a pair of fins;
forming first and second spacers on opposite sides of the first and second upper portions, respectively;
removing the metal layer between adjacent first and second spacers;
forming an interlayer dielectric (ILD) over the substrate; and
forming a source/drain contact (CA) on each upper portion and a gate contact (CB) on one of the two gates through the ILD.

2. The method according to claim 1 , comprising forming each of the two gates as a high-k metal gate (HKMG).

3. The method according to claim 1 , comprising forming the first and second pairs of RSD by epitaxial growth.

4. The method according to claim 1 , further comprising:
forming a liner over and between the first and second pairs of RSD;
forming an ILD over the first and second pairs of RSD and between the two gates prior to forming the SAC cap; and
removing the ILD between the two gates by highly selective isotropic etching after forming the SAC caps.

5. The method according to claim 4 , comprising removing the liner from upward facing portions of the first and second pairs of RSD and between the first and second pairs.

6. The method according to claim 1 , comprising forming the metal layer by:
forming a blanket silicide layer over the substrate;
forming the metal layer over the silicide layer; and
planarizing the metal layer down to the upper surface of the SAC caps.

7. The method according to claim 1 , comprising:
etching the metal layer proximate to the oxide and nitride stacks to a thickness of 5 nanometer (nm) to 15 nm.

8. The method according to claim 7 , further comprising:
forming an etch stop liner over the oxide and nitride stacks and the metal layer; and
removing the etch stop liner from the metal layer and the oxide and nitride stacks subsequent to forming the spacers on opposite sides of each TS structure upper portion.

9. The method according to claim 8 , comprising forming the spacers on opposite sides of each TS structure upper portion by:
filling spaces between the upper portions with oxide;
forming a conformal oxide layer over and between the oxide and nitride stacks; and
etching the oxide layer by reactive ion etching (RIE), the etch selective to nitride.

10. The method according to claim 9 , comprising etching the oxide layer until the spacers have a width of 6 nm to 10 nm.

11. The method according to claim 1 , comprising forming the ILD by:
forming a first oxide layer over the substrate;
planarizing the first oxide layer down to the upper surface of the SACs; and
forming a second oxide layer over the first oxide layer.

12. A method comprising:
forming two high-k metal gates (HKMGs) across and perpendicular to first and second pairs of fins formed through a shallow trench isolation (STI) layer on a substrate;
epitaxially growing first and second pairs of raised source/drain (RSD) between the first and second gates on first and second pairs of fins, respectively;
forming a planar self-aligned contact (SAC) cap on each metal gate;
forming a liner on downward facing surfaces of each RSD;
forming a blanket silicide layer over the substrate;
forming a metal layer over the silicide layer;
planarizing the metal layer down to an upper surface of the SACs;
forming an oxide layer over the substrate subsequent to forming the metal layer;
forming a nitride layer over the oxide layer;
patterning the oxide and nitride layers, forming first and second oxide and nitride stacks above the first and second pairs of RSD, respectively, the first and second oxide and nitride stacks being perpendicular to the two HKMGs and each having with a width equal to or less than an overall width of a pair of fins;
etching the metal layer proximate to the oxide and nitride stacks forming trench silicide (TS) structure upper portions above the first and second pairs of RSD, and forming the TS structure in the metal layer over and perpendicular to the fins, the TS structure having first and second upper portions over the first and second pairs of RSD, respectively, each upper portion having a width equal to or less than an overall width of a pair of fins;
forming second spacers on opposite sides of each upper portion of each TS structure;
removing the metal layer proximate to each second spacer;
forming a first oxide layer over the substrate;
planarizing the first oxide layer down to the upper surface of the SACs;
forming a second oxide layer over the first oxide layer; and
forming a source/drain contact (CA) on each upper portion and a gate contact (CB) on one of the two HKMGs through the second oxide layer.

13. The method according to claim 12 , comprising:
etching the metal layer proximate to the oxide and nitride stacks to a thickness of 5 nanometer (nm) to 15 nm.

14. The method according to claim 13 , further comprising:
forming an etch stop liner over the oxide and nitride stacks and the metal layer; and
removing the etch stop liner from the metal layer and the oxide and nitride stacks subsequent to the second spacer formation.

15. The method according to claim 14 , comprising forming the second spacers on opposite sides of each TS structure upper portion by:
filing spacers between the upper portions with oxide;
forming a conformal oxide layer over and between the oxide and nitride stacks; and
etching the oxide layer by reactive ion etching (RIE), the etch selective to nitride until each of the second spacers have a width of 6 nm to 10 nm.

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Chanemougame Daniel
• Liebmann Lars
• Cave Nigel

Classifications

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title