System and method for filtering field programmable gate array input/output

Patent metadata

Field	Value
Publication number	US-10248585-B2
Application number	US-201615182005-A
Country	US
Kind code	B2
Filing date	Jun 14, 2016
Priority date	Jun 14, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.

First claim

We claim:

1. A method comprising:
receiving a Field Programmable Gate Array (FPGA) program bitstream;
generating, based at least in part on the FPGA bitstream, FPGA programming logic segments;
modifying, based at least in part on the FPGA programming logic segments, an FPGA to comprise a core logic layer and a filtering layer;
receiving, by the filtering layer, Input/Output (I/O) associated with the core logic layer;
modifying, based at least in part on the filtering layer, the I/O associated with the core logic layer;
that the
sampling the I/O associated with the core logic layer to generate a sampled I/O;
receiving, at a processor, a timestamp from the FPGA associated with the sampled I/O;
receiving, at the processor, an interrupt signal associated with the FPGA; and
in response to receiving the interrupt signal, correlating the sampled I/O and the timestamp with an Epoch time of the processor.

2. The method of claim 1 , wherein the I/O associated with the core logic layer comprises one of signals associated with pins of the FPGA, signals embedded inside a serial GPIO interface, or signals of or any other buses.

3. The method of claim 1 , further comprising passing the modified I/O associated with the core logic layer through the filtering layer.

4. The method of claim 1 , further comprising:
identifying a trigger; and
in response to detecting the trigger:
storing the sampled I/O in a FPGA blockRAM.

5. The method of claim 4 , wherein the trigger is an error condition.

6. The method of claim 1 , wherein the timestamp from the FPGA is calibrated by the processor.

7. A system comprising:
a processor;
a Field Programmable Gate Array (FPGA); and
a computer-readable storage medium having instructions stored which, when executed by the processor, cause the processor to perform operations comprising:
receiving a FPGA program bitstream;
generating, based at least in part on the FPGA bitstream, FPGA programming logic segments;
modifying, based at least in part on the FPGA programming logic segments, the FPGA to comprise a core logic layer and a filtering layer;
receiving, a timestamp from the FPGA associated with a sampled Input/Output (I/O), wherein the sampled I/O is a sample of an I/O associated with the core logic layer;
receiving an interrupt signal associated with the FPGA; and
in response to receiving the interrupt signal, correlating the sampled I/O and the timestamp with an Epoch time of the processor.

8. The system of claim 7 , wherein the I/O associated with the core logic layer comprises one of signals associated with pins of the FPGA, signals embedded inside a serial GPIO interface, or signals of or any other buses.

9. The system of claim 7 , wherein the modified FPGA performs operations comprising passing the I/O associated with the core logic layer through the filtering.

10. The system of claim 7 , the computer-readable storage medium having additional instructions stored which, when executed by the processor, cause the processor to perform operations comprising:
identifying a trigger; and
in response to detecting the trigger:
storing the sampled I/O in a FPGA blockRAM.

11. The system of claim 10 , wherein the trigger is an error condition.

12. The system of claim 7 , wherein the timestamp from the FPGA is calibrated by the processor.

13. A computer-readable storage device having instructions stored which, when executed by a computing device, cause the computing device to perform operations comprising:
receiving a Field Programmable Gate Array (FPGA) program bitstream;
generating, based at least in part on the FPGA bitstream, FPGA programming logic segments;
modifying, based at least in part on the FPGA programming logic segments, the FPGA to comprise a core logic layer and a filtering layer;
receiving, a timestamp from the FPGA associated with a sampled Input/Output (I/O), wherein the sampled I/O is a sample of an I/O associated with the core logic layer;
receiving an interrupt signal associated with the FPGA; and
in response to receiving the interrupt signal, correlating the sampled I/O and the timestamp with an Epoch time of the computing device.

14. The computer-readable storage device of claim 13 , wherein the I/O associated with the core logic layer comprises one of signals associated with pins of the FPGA, signals embedded inside a serial GPIO interface, or signals of or any other buses.

15. The computer-readable storage device of claim 13 , wherein the modified FPGA is configured to pass the I/O through the filtering layer.

Assignees

• Oracle Int Corp

Inventors

• Ma Xianda
• Derbish Michael David
• Edeltraut Koch-Stoschek Cornelia Luise
• Lolabattu Rambabu
• Poon Simon yiu hoi
• Yang Cheng

Classifications

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F11/3034

  where the computing system component is a storage system, e.g. DASD based or network based (digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• H03K19/1776 Primary

  for memories · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F11/3072

  where the reporting involves data filtering, e.g. pattern matching, time or event triggered, adaptive or policy-based reporting · CPC title