Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCS)

Patent metadata

Field	Value
Publication number	US-10243576-B2
Application number	US-201815974756-A
Country	US
Kind code	B2
Filing date	May 9, 2018
Priority date	Aug 10, 2012
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC), comprising:
a comparator comprising an analog input, a reference input, a preemption input, a codeword output, and a validation output, wherein the validation output indicates a valid decision and the codeword output indicates a comparison between the analog input and the reference input when a preemption is not indicated at the preemption input;
a digital-to-analog converter (DAC) comprising a codeword input and a reference output, wherein the reference output of the DAC is operably coupled to the reference input of the comparator and the codeword input of the DAC is operably coupled to the codeword output of the comparator; and
a timer operable to set a preemption output in time according to a validation input, wherein the validation input of the timer is operably coupled to the validation output of the comparator and the preemption output of the timer is operably coupled to the preemption input of the comparator.

2. The ADC according to claim 1 , wherein the comparator is operable to determine one or more bits of a codeword according to one or more comparisons.

3. The ADC according to claim 2 , wherein one or more least significant bits of the codeword are derived from a value of a bit that was determined in an immediately preceding comparison.

4. The ADC according to claim 1 , wherein the timer is operable to indicate a preemption at the preemption output based on a adaptively-determined threshold time.

5. The ADC according to claim 4 , wherein the adaptively-determined threshold time is determined according to a time required for a difference between the analog input and the reference input to be less that a predetermined threshold.

6. The ADC according to claim 5 , wherein the predetermined threshold is based on one or more overlapping redundant bits.

7. The ADC according to claim 5 , wherein the comparator is operable to map a comparing time for each comparison to a difference between the analog input and the reference input.

8. The ADC according to claim 7 , wherein the comparator is operable to calibrate results from the mapping based on process, temperature and/or variations in the analog input.

9. The ADC according to claim 8 , wherein the comparator is operable to store the results from the mapping and results from the calibrating.

10. The ADC according to claim 7 , wherein the DAC is operable to set a particular value for a next bit if the comparing time of each comparison exceeds a particular time.

11. A method, comprising:
comparing an analog signal to a reference signal to determine one or more bits of a codeword, the codeword on the codeword comprising one or more overlapping redundant bits;
indicating a valid decision if a preemption is not indicated;
generating the reference signal according to the codeword using a digital-to-analog converter (DAC); and
setting the preemption according to a timer and the validation signal.

12. The method according to claim 11 , wherein the method is performed iteratively.

13. The method according to claim 12 , wherein the method comprises determining one or more least significant bits of the codeword according to a value of a bit that was determined in an immediately preceding iteration.

14. The method according to claim 11 , wherein the method comprises indicating the preemption based on a adaptively-determined threshold time.

15. The method according to claim 14 , wherein the method comprises determining the adaptively-determined threshold time according to a time required for a difference between the analog input and the reference input to be less that a predetermined threshold.

16. The method according to claim 15 , wherein the predetermined threshold is based on the one or more overlapping redundant bits.

17. The method according to claim 15 , wherein the method comprises mapping a comparing time for each comparison to a difference between the analog input and the reference input.

18. The method according to claim 17 , wherein the method comprises calibrating results from the mapping based on process, temperature and/or variations in the analog input.

19. The method according to claim 18 , wherein the method comprises storing the results from the mapping and results from the calibrating.

20. The method according to claim 17 , wherein the method comprises setting a particular value for a next bit if the comparing time of each comparison exceeds a particular time.

Assignees

• Maxlinear Inc

Inventors

• Fogleman Eric
• Ye Sheng
• Chen Xuefeng
• Chan Kok Lim

Classifications

• H03M1/0617 Primary

  characterised by the use of methods or means not specific to a particular type of detrimental influence · CPC title

• H03M1/46 Primary

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/069

  by range overlap between successive stages or steps · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/001

  Analogue/digital/analogue conversion · CPC title