Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs)

Patent metadata

Field	Value
Publication number	US-9800253-B2
Application number	US-201615230735-A
Country	US
Kind code	B2
Filing date	Aug 8, 2016
Priority date	Aug 10, 2012
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC), comprising:
a digital-to-analog converter (DAC) comprising a codeword input and a reference output;
a comparator comprising an analog input, a reference input, a preemption input, a codeword output, and a validation output, the reference input of the comparator being operably coupled to the reference output of the DAC, the codeword output of the comparator being operably coupled to the codeword input of the DAC, wherein:
a codeword on the codeword output of the comparator comprises one or more overlapping redundant bits,
when a preemption signal on the preemption input indicates a preemption, a validation signal on the validation output is set to indicate the preemption and one or more bits of the codeword are set to a particular value, and
when the preemption signal on the preemption input does not indicate a preemption, the validation signal on the validation output is set to indicate a valid decision and one or more bits of the codeword are set according to a comparison between the analog input and the reference input; and

a timer comprising a validation input and a preemption output, the validation input of the timer being operably coupled to the validation output of the comparator, the preemption output of the timer being operably coupled to the preemption input of the comparator, the preemption signal being set in time according to the validation signal.

2. The ADC according to claim 1 , wherein the comparator is operable to set one or more least significant bits of the codeword up to, but not including, the one or more overlapping redundant bits in the codeword for a current comparison step, the one or more least significant bits being set to a value derived from a value of a bit that was determined in an immediately preceding decision.

3. The ADC according to claim 1 , wherein the timer is operable to generate the timeout signal based on a dynamically and/or adaptively determined threshold time.

4. The ADC according to claim 3 , wherein the determined threshold time is selected so as to guarantee that a magnitude of a difference between the analog input and the reference input is within an overlapping range corresponding to the one or more overlapping redundant bits.

5. The ADC according to claim 1 , wherein the comparator is operable to compare, for each of a plurality of comparison steps, the analog input to the reference input.

6. The ADC according to claim 5 , wherein the comparator is operable to map a corresponding comparing time for each comparison step to a difference between the analog input and the reference input.

7. The ADC according to claim 6 , wherein the comparator is operable to calibrate results from the mapping based on process, temperature and/or variations in the analog input.

8. The ADC according to claim 7 , wherein the comparator is operable to store the results from the mapping and results from the calibrating.

9. The ADC according to claim 5 , wherein the DAC is operable to set a particular value for a next bit if the corresponding comparing time of each comparison step exceeds a particular time.

10. The ADC according to claim 9 , wherein the difference between the analog input and the reference input is a fractional portion, the fractional portion comprising ½, ¼, ⅛, 1/16 and/or 1/32.

11. A method for analog-to-digital conversion, comprising:
converting a codeword to a reference value, using a digital-to-analog converter (DAC), wherein the codeword comprises one or more overlapping redundant bits;
when a preemption signal, input to a comparator, indicates a preemption, setting a validation signal, output from the comparator, to indicate the preemption and setting one or more bits of the codeword, output from the comparator, to a particular value;
when the preemption signal, input to the comparator, does not indicate a preemption, setting the validation signal, output from the comparator, to indicate a valid decision and setting one or more bits of the codeword, output from the comparator, according to a comparison between an analog input and the reference value; and
setting the preemption signal in time, using a timer, according to the validation signal.

12. The method according to claim 11 , wherein the method further comprises setting one or more least significant bits of the codeword up to, but not including, the one or more overlapping redundant bits in the codeword to a value derived from a value of a bit that was determined in an immediately preceding decision.

13. The method according to claim 11 , wherein the method further comprises generating a timeout signal based on a dynamically and/or adaptively determined threshold time.

14. The method according to claim 13 , wherein the method further comprises selecting the determined threshold time so as to guarantee that a magnitude of a difference between the analog input and the reference value is within an overlapping range corresponding to the one or more overlapping redundant bits.

15. The method according to claim 11 , wherein the method further comprises comparing, for each of a plurality of comparison steps, the analog input to the reference value.

16. The method according to claim 15 , wherein the method further comprises mapping a corresponding comparing time for each comparison step to a difference between the analog input and the reference value.

17. The method according to claim 16 , wherein the method further comprises calibrating results from the mapping based on process, temperature and/or variations in the analog input.

18. The method according to claim 17 , wherein the method further comprises storing the results from the mapping and results from the calibrating.

19. The method according to claim 15 , wherein the method further comprises setting a next bit to a particular value if the corresponding comparing time of each preceding comparison step exceeds a particular time.

20. The method according to claim 19 , wherein the particular value is a fractional value.

Assignees

• Maxlinear Inc

Inventors

• Fogleman Eric
• Ye Sheng
• Chen Xuefeng
• Chan Kok Lim

Classifications

• H03M1/001

  Analogue/digital/analogue conversion · CPC title

• H03M1/0617 Primary

  characterised by the use of methods or means not specific to a particular type of detrimental influence · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/069

  by range overlap between successive stages or steps · CPC title

• H03M1/46 Primary

  with digital/analogue converter for supplying reference values to converter · CPC title