Counter circuitry and method

Patent metadata

Field	Value
Publication number	US-10763829-B2
Application number	US-201715683962-A
Country	US
Kind code	B2
Filing date	Aug 23, 2017
Priority date	Aug 23, 2017
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

First claim

We claim:

1. Apparatus comprising:
master counter circuitry to generate a master count signal in response to a clock signal;
slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and
a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry;
the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value, wherein the master counter circuitry is configured to provide the data indicative of the count offset value before providing the timing signal, wherein the data indicative of the count offset value indicates a future count value applicable at a time that the timing signal is provided to the slave counter circuitry; and
the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and the timing signal provided by the master counter circuitry.

2. Apparatus according to claim 1 , in which the synchronisation connection provides serial communication of the data indicative of a count offset value and the timing signal.

3. Apparatus according to claim 2 , in which the synchronisation connection comprises a single conductive path from the master counter circuitry to the slave counter circuitry.

4. Apparatus according to claim 1 , in which the master counter circuitry comprises an offset generator configured to generate the count offset value in response to:
a current state of the master count signal; and
a time period to transmit the count offset value via the synchronisation connection.

5. Apparatus according to claim 1 , comprising:
power management circuitry to control transitions of the slave counter circuitry between an operational state and a quiescent state.

6. Apparatus according to claim 5 , the apparatus being configured to initiate a synchronisation operation for a slave counter circuitry in response to a transition of that slave counter circuitry from the quiescent to the operational state.

7. Apparatus according to claim 6 , comprising one or more processing elements configured to perform processing operations in response to the slave count signal, the power management circuitry being configured to control transitions of the one or more processing elements between an operational state and a quiescent state.

8. Apparatus according to claim 7 , in which the power management circuitry is configured to control a transition of the one or more processing elements from the quiescent state to an operational state in response to completion of the synchronisation operation for the slave counter circuitry.

9. Apparatus according to claim 8 , in which the power management circuitry is configured to indicate to the master counter circuitry that a synchronisation operation should be started, in response to initiation of a transition of the slave counter circuitry from the quiescent state to the operational state.

10. Apparatus according to claim 8 , in which:
the master counter circuitry is configured to indicate to the power management circuitry that a synchronisation operation has completed; and
the power management circuitry is configured to initiate a transition of the one or more processing elements from the quiescent to the operational state in response to the master counter circuitry indicating that a synchronisation operation has completed.

11. Apparatus according to claim 10 , in which:
the master counter circuitry comprises a register configured to store a data item indicative of whether a synchronisation operation should be started;
the power management circuitry is configured to write data to the register to indicate that a synchronisation operation should be started; and
the master counter circuitry is configured to store a data item in the register to indicate that a synchronisation operation has completed.

12. Apparatus according to claim 1 , in which:
the slave counter circuitry is configure to count according to count increments defined by a scaling value; and
the master counter circuitry is configured to provide the scaling value to the slave counter circuitry via the synchronisation connection, during a synchronisation operation for that slave counter circuitry.

13. Apparatus according to claim 1 , in which the master counter circuitry is configured to supply the clock signal to the slave counter circuitry.

14. Apparatus according to claim 5 , comprising two or more slave counter circuitries, separately controllable by the power management circuitry between the quiescent state and the operational state.

15. An integrated circuit comprising apparatus according to claim 1 .

16. Apparatus comprising:
means for generating a master count signal in response to a clock signal;
means for generating a slave count signal in response to the clock signal; and
means for providing signal communication between the means for generating a master count signal and the means for generating a slave count signal;
the means for generating a master count signal being operable to provide to the means for generating a slave count signal via the means for providing signal communication: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value, wherein the means for generating a master count signal is configured to provide the data indicative of the count offset value before providing the timing signal, wherein the data indicative of the count offset value indicates a future count value applicable at a time that the timing signal is provided to the slave counter circuitry; and
the means for generating a slave count signal being operable, during a synchronisation operation for that means for generating a slave count signal, to initialise a counting operation of that means for generating a slave count signal in response to the data indicative of the count offset value and the timing signal provided by the means for generating a master count signal.

17. A method comprising:
master counter circuitry generating a master count signal in response to a clock signal;
the master counter circuitry providing to slave counter circuitry via a synchronisation connection: data indicative of a count offset value and a timing signal defining a timing relationship between the clock signal and the count offset value, wherein the master counter circuitry provides the data indicative of the count offset value before providing the timing signal wherein the data indicative of the count offset value indicates a future count value applicable at a time that the timing signal is provided to the slave counter circuitry;
the slave counter circuitry, during a synchronisation operation for that slave counter circuitry, initialising a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and the timing signal provided by the master counter circuitry; and
the slave counter circuitry generating a slave count signal in response to the clock signal.

18. Apparatus according to claim 1 , wherein the data indicative of a count offset value and the timing signal defining a timing relationship between the clock signal and the count offse

Assignees

• Advanced Risc Mach Ltd

Inventors

• Crawford Ashley John
• Horley John Michael

Classifications

• H03K21/406 Primary

  Synchronisation of counters · CPC title

• H03B5/12

  active element in amplifier being semiconductor device (H03B5/14 takes precedence) · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G07C3/04

  using counting means or digital clocks · CPC title

• H03K9/06

  of frequency- or rate-modulated pulses · CPC title